Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14300084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59390719

1

T1

18579

T2

8767

T3

91808

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36723697	1			T1	10237		T2	4760		T3	50640
values[0x0]	17048817	1			T1	4926		T2	2330		T3	24224
values[0x1]	19918289	1			T1	5337		T2	2552		T3	26085

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7120029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66570774

1

T1

19540

T2

9174

T3

96335

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	267065	1			T2	29		T3	318		T7	759
valid_sources[0x01]	292497	1			T2	30		T3	450		T7	913
valid_sources[0x02]	283405	1			T2	41		T3	439		T7	777
valid_sources[0x03]	265542	1			T2	14		T3	293		T7	863
valid_sources[0x04]	401933	1			T2	46		T3	389		T7	869
valid_sources[0x05]	274674	1			T2	69		T3	385		T7	1066
valid_sources[0x06]	297444	1			T2	39		T3	323		T7	980
valid_sources[0x07]	306643	1			T2	15		T3	352		T7	854
valid_sources[0x08]	250673	1			T2	26		T3	349		T7	920
valid_sources[0x09]	276658	1			T2	23		T3	553		T7	798
valid_sources[0x0a]	273931	1			T2	41		T3	264		T7	962
valid_sources[0x0b]	277278	1			T1	2147		T2	46		T3	455
valid_sources[0x0c]	253784	1			T2	27		T3	362		T7	847
valid_sources[0x0d]	334097	1			T2	19		T3	393		T7	781
valid_sources[0x0e]	276590	1			T2	31		T3	312		T7	833
valid_sources[0x0f]	307480	1			T2	22		T3	417		T7	634
valid_sources[0x10]	324632	1			T2	30		T3	422		T7	855
valid_sources[0x11]	308868	1			T2	30		T3	393		T7	620
valid_sources[0x12]	288112	1			T2	64		T3	414		T7	827
valid_sources[0x13]	313018	1			T2	31		T3	365		T7	1002
valid_sources[0x14]	252742	1			T2	30		T3	342		T7	733
valid_sources[0x15]	307161	1			T2	21		T3	472		T7	777
valid_sources[0x16]	270104	1			T2	62		T3	401		T7	768
valid_sources[0x17]	267932	1			T2	35		T3	460		T7	805
valid_sources[0x18]	261071	1			T2	31		T3	475		T7	754
valid_sources[0x19]	309084	1			T2	35		T3	391		T7	770
valid_sources[0x1a]	264552	1			T2	34		T3	372		T7	1087
valid_sources[0x1b]	322292	1			T2	60		T3	465		T7	1028
valid_sources[0x1c]	347088	1			T2	60		T3	417		T7	1046
valid_sources[0x1d]	355379	1			T2	24		T3	418		T7	839
valid_sources[0x1e]	303287	1			T2	24		T3	360		T7	623
valid_sources[0x1f]	366297	1			T2	31		T3	328		T7	866
valid_sources[0x20]	383014	1			T2	47		T3	463		T7	777
valid_sources[0x21]	306106	1			T2	33		T3	298		T7	685
valid_sources[0x22]	309129	1			T2	56		T3	353		T7	627
valid_sources[0x23]	305998	1			T2	28		T3	384		T7	1072
valid_sources[0x24]	310896	1			T2	26		T3	417		T7	779
valid_sources[0x25]	256113	1			T2	39		T3	413		T7	753
valid_sources[0x26]	260882	1			T2	33		T3	406		T7	859
valid_sources[0x27]	335754	1			T2	60		T3	383		T7	607
valid_sources[0x28]	361003	1			T2	13		T3	314		T7	928
valid_sources[0x29]	253698	1			T2	58		T3	402		T7	844
valid_sources[0x2a]	269002	1			T2	45		T3	372		T7	690
valid_sources[0x2b]	252753	1			T2	37		T3	404		T7	885
valid_sources[0x2c]	268541	1			T2	25		T3	360		T7	629
valid_sources[0x2d]	249056	1			T2	56		T3	492		T7	907
valid_sources[0x2e]	271796	1			T2	70		T3	418		T7	536
valid_sources[0x2f]	278764	1			T2	12		T3	473		T7	1030
valid_sources[0x30]	305469	1			T2	29		T3	331		T7	979
valid_sources[0x31]	292912	1			T2	55		T3	309		T7	655
valid_sources[0x32]	273108	1			T2	35		T3	266		T7	1005
valid_sources[0x33]	250176	1			T2	42		T3	475		T7	856
valid_sources[0x34]	254628	1			T2	33		T3	475		T7	857
valid_sources[0x35]	306975	1			T2	36		T3	264		T7	746
valid_sources[0x36]	313377	1			T2	26		T3	421		T7	851
valid_sources[0x37]	255489	1			T2	38		T3	303		T7	985
valid_sources[0x38]	329770	1			T2	27		T3	432		T7	923
valid_sources[0x39]	238940	1			T2	48		T3	459		T7	732
valid_sources[0x3a]	264286	1			T2	16		T3	422		T7	957
valid_sources[0x3b]	331041	1			T2	48		T3	375		T7	942
valid_sources[0x3c]	251963	1			T2	39		T3	382		T7	606
valid_sources[0x3d]	294451	1			T2	30		T3	352		T7	898
valid_sources[0x3e]	295068	1			T2	49		T3	474		T7	970
valid_sources[0x3f]	432572	1			T2	17		T3	510		T7	1178
valid_sources[0x40]	324848	1			T2	13		T3	376		T7	729
valid_sources[0x41]	303225	1			T2	55		T3	315		T7	827
valid_sources[0x42]	242240	1			T2	9		T3	555		T7	1107
valid_sources[0x43]	295703	1			T2	33		T3	318		T7	655
valid_sources[0x44]	261703	1			T2	45		T3	463		T7	868
valid_sources[0x45]	289891	1			T2	50		T3	292		T7	801
valid_sources[0x46]	254476	1			T2	30		T3	423		T7	722
valid_sources[0x47]	316027	1			T2	20		T3	536		T7	906
valid_sources[0x48]	299627	1			T2	35		T3	475		T7	867
valid_sources[0x49]	289043	1			T2	53		T3	413		T7	875
valid_sources[0x4a]	248912	1			T2	28		T3	460		T7	697
valid_sources[0x4b]	322223	1			T2	23		T3	381		T7	955
valid_sources[0x4c]	324612	1			T2	36		T3	280		T7	760
valid_sources[0x4d]	294879	1			T2	15		T3	273		T7	1061
valid_sources[0x4e]	276429	1			T2	34		T3	535		T7	498
valid_sources[0x4f]	295159	1			T2	54		T3	322		T7	915
valid_sources[0x50]	274425	1			T2	34		T3	477		T7	772
valid_sources[0x51]	241996	1			T2	25		T3	305		T7	778
valid_sources[0x52]	269495	1			T2	52		T3	330		T7	819
valid_sources[0x53]	283772	1			T2	21		T3	341		T7	670
valid_sources[0x54]	248457	1			T2	41		T3	402		T7	911
valid_sources[0x55]	268629	1			T2	38		T3	378		T7	652
valid_sources[0x56]	276208	1			T2	47		T3	400		T7	1019
valid_sources[0x57]	286667	1			T2	13		T3	368		T7	971
valid_sources[0x58]	356945	1			T2	54		T3	285		T7	713
valid_sources[0x59]	377904	1			T2	27		T3	407		T7	842
valid_sources[0x5a]	269411	1			T2	39		T3	386		T7	835
valid_sources[0x5b]	266917	1			T2	43		T3	467		T7	592
valid_sources[0x5c]	284807	1			T2	48		T3	373		T7	958
valid_sources[0x5d]	381803	1			T2	24		T3	506		T7	824
valid_sources[0x5e]	288334	1			T2	26		T3	364		T7	676
valid_sources[0x5f]	255138	1			T2	30		T3	286		T7	1033
valid_sources[0x60]	294792	1			T2	37		T3	343		T7	731
valid_sources[0x61]	270165	1			T2	38		T3	451		T7	967
valid_sources[0x62]	262532	1			T2	17		T3	376		T7	723
valid_sources[0x63]	273424	1			T2	32		T3	281		T7	963
valid_sources[0x64]	371978	1			T2	21		T3	433		T7	947
valid_sources[0x65]	291552	1			T2	61		T3	488		T7	778
valid_sources[0x66]	312049	1			T2	45		T3	359		T7	717
valid_sources[0x67]	321372	1			T2	56		T3	406		T7	640
valid_sources[0x68]	281700	1			T2	33		T3	377		T7	791
valid_sources[0x69]	290584	1			T2	48		T3	385		T7	1056
valid_sources[0x6a]	263414	1			T2	40		T3	301		T7	803
valid_sources[0x6b]	271130	1			T2	58		T3	264		T7	858
valid_sources[0x6c]	276663	1			T2	33		T3	437		T7	707
valid_sources[0x6d]	260616	1			T2	30		T3	405		T7	726
valid_sources[0x6e]	288120	1			T2	59		T3	421		T7	654
valid_sources[0x6f]	284814	1			T2	44		T3	282		T7	772
valid_sources[0x70]	253942	1			T2	34		T3	345		T7	883
valid_sources[0x71]	282995	1			T2	12		T3	310		T7	868
valid_sources[0x72]	249993	1			T2	44		T3	364		T7	1038
valid_sources[0x73]	261846	1			T2	34		T3	434		T7	1084
valid_sources[0x74]	258387	1			T2	30		T3	351		T7	914
valid_sources[0x75]	281750	1			T2	50		T3	333		T7	690
valid_sources[0x76]	327544	1			T2	17		T3	383		T7	1026
valid_sources[0x77]	268874	1			T2	42		T3	387		T7	687
valid_sources[0x78]	270735	1			T2	29		T3	365		T7	847
valid_sources[0x79]	249770	1			T2	28		T3	453		T7	809
valid_sources[0x7a]	254517	1			T2	28		T3	395		T7	893
valid_sources[0x7b]	345418	1			T2	40		T3	364		T7	984
valid_sources[0x7c]	268918	1			T2	57		T3	314		T7	673
valid_sources[0x7d]	331054	1			T2	29		T3	479		T7	726
valid_sources[0x7e]	276699	1			T2	18		T3	429		T7	719
valid_sources[0x7f]	257910	1			T2	40		T3	400		T7	660
valid_sources[0x80]	259581	1			T2	17		T3	341		T7	692

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29576584

1

T1

9280

T2

4304

T3

45961

values[0x0]

all_enables

biggest_size

14902506

1

T1

4639

T2

2199

T3

22867

values[0x1]

all_enables

biggest_size

14911629

1

T1

4660

T2

2264

T3

22980

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162731

1

T2

2

T3

3

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57297	1			T4	8		T25	7		T5	30
values[0x0]	68610	1			T1	1		T2	2		T3	11
values[0x1]	74520	1			T1	1		T3	7		T7	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172439

1

T2

2

T3

6

T7

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	758	1			T3	1		T26	22		T17	1
valid_sources[0x01]	876	1			T66	2		T26	7		T23	1
valid_sources[0x02]	811	1			T26	14		T153	2		T35	1
valid_sources[0x03]	554	1			T42	1		T26	28		T23	1
valid_sources[0x04]	838	1			T26	20		T154	1		T132	1
valid_sources[0x05]	577	1			T26	31		T119	5		T135	3
valid_sources[0x06]	744	1			T26	20		T155	2		T28	13
valid_sources[0x07]	747	1			T57	1		T26	22		T82	1
valid_sources[0x08]	1195	1			T26	35		T80	1		T35	1
valid_sources[0x09]	763	1			T26	37		T23	4		T152	1
valid_sources[0x0a]	1079	1			T65	2		T26	9		T35	1
valid_sources[0x0b]	996	1			T1	2		T156	4		T26	20
valid_sources[0x0c]	1016	1			T26	14		T101	1		T157	1
valid_sources[0x0d]	642	1			T26	7		T100	1		T35	1
valid_sources[0x0e]	808	1			T26	16		T82	1		T153	1
valid_sources[0x0f]	555	1			T46	1		T26	26		T23	1
valid_sources[0x10]	1280	1			T26	19		T100	2		T152	1
valid_sources[0x11]	712	1			T3	1		T20	1		T26	13
valid_sources[0x12]	1007	1			T26	22		T79	1		T153	2
valid_sources[0x13]	523	1			T26	11		T79	1		T100	1
valid_sources[0x14]	758	1			T3	1		T4	1		T26	27
valid_sources[0x15]	647	1			T26	10		T17	4		T152	2
valid_sources[0x16]	1035	1			T10	1		T6	3		T26	21
valid_sources[0x17]	996	1			T26	20		T23	2		T152	4
valid_sources[0x18]	585	1			T42	1		T26	18		T135	1
valid_sources[0x19]	536	1			T26	26		T16	1		T39	2
valid_sources[0x1a]	781	1			T26	25		T135	1		T35	1
valid_sources[0x1b]	1139	1			T65	2		T26	33		T80	2
valid_sources[0x1c]	808	1			T42	1		T26	27		T153	1
valid_sources[0x1d]	877	1			T26	18		T100	1		T35	1
valid_sources[0x1e]	707	1			T4	1		T51	1		T26	10
valid_sources[0x1f]	968	1			T26	18		T79	1		T23	3
valid_sources[0x20]	545	1			T30	1		T26	14		T120	2
valid_sources[0x21]	645	1			T116	1		T66	1		T26	13
valid_sources[0x22]	722	1			T4	1		T26	27		T82	1
valid_sources[0x23]	1157	1			T4	1		T26	26		T79	1
valid_sources[0x24]	709	1			T117	1		T26	12		T82	3
valid_sources[0x25]	1110	1			T26	14		T152	2		T28	28
valid_sources[0x26]	578	1			T66	2		T26	23		T23	2
valid_sources[0x27]	587	1			T26	12		T84	1		T23	2
valid_sources[0x28]	966	1			T66	2		T26	21		T129	1
valid_sources[0x29]	742	1			T26	23		T100	1		T152	1
valid_sources[0x2a]	1109	1			T26	16		T135	1		T16	3
valid_sources[0x2b]	731	1			T26	20		T152	2		T27	80
valid_sources[0x2c]	739	1			T5	5		T26	16		T129	1
valid_sources[0x2d]	566	1			T26	10		T153	1		T35	1
valid_sources[0x2e]	685	1			T43	1		T26	12		T152	4
valid_sources[0x2f]	652	1			T26	12		T158	1		T159	1
valid_sources[0x30]	730	1			T26	5		T135	1		T159	2
valid_sources[0x31]	810	1			T26	15		T160	2		T100	1
valid_sources[0x32]	737	1			T6	6		T26	24		T135	2
valid_sources[0x33]	713	1			T26	25		T23	3		T100	3
valid_sources[0x34]	707	1			T58	1		T43	2		T26	14
valid_sources[0x35]	710	1			T26	15		T100	1		T35	1
valid_sources[0x36]	783	1			T26	15		T82	1		T152	2
valid_sources[0x37]	1007	1			T10	1		T26	25		T83	2
valid_sources[0x38]	874	1			T3	1		T26	16		T79	1
valid_sources[0x39]	1091	1			T26	9		T100	1		T16	1
valid_sources[0x3a]	1097	1			T26	29		T23	1		T86	2
valid_sources[0x3b]	664	1			T20	1		T26	8		T23	2
valid_sources[0x3c]	557	1			T26	32		T80	2		T86	1
valid_sources[0x3d]	583	1			T20	2		T26	16		T35	2
valid_sources[0x3e]	894	1			T26	20		T23	3		T135	2
valid_sources[0x3f]	687	1			T42	1		T26	31		T160	1
valid_sources[0x40]	590	1			T26	16		T153	1		T17	2
valid_sources[0x41]	660	1			T45	2		T66	1		T26	21
valid_sources[0x42]	1079	1			T26	8		T23	6		T135	1
valid_sources[0x43]	832	1			T51	1		T26	22		T23	3
valid_sources[0x44]	929	1			T3	3		T26	12		T86	4
valid_sources[0x45]	1151	1			T26	9		T23	1		T35	1
valid_sources[0x46]	818	1			T4	1		T20	1		T26	8
valid_sources[0x47]	819	1			T20	1		T26	16		T135	1
valid_sources[0x48]	546	1			T6	4		T26	20		T23	1
valid_sources[0x49]	561	1			T51	1		T26	24		T82	1
valid_sources[0x4a]	817	1			T26	18		T80	1		T23	4
valid_sources[0x4b]	722	1			T161	1		T26	20		T85	28
valid_sources[0x4c]	767	1			T26	22		T23	2		T159	1
valid_sources[0x4d]	625	1			T26	19		T100	1		T35	1
valid_sources[0x4e]	945	1			T26	24		T55	3		T86	6
valid_sources[0x4f]	717	1			T26	10		T152	1		T157	3
valid_sources[0x50]	659	1			T26	18		T80	2		T23	1
valid_sources[0x51]	992	1			T26	12		T159	1		T152	1
valid_sources[0x52]	540	1			T66	7		T26	12		T135	2
valid_sources[0x53]	637	1			T26	32		T79	1		T28	6
valid_sources[0x54]	712	1			T26	15		T153	2		T17	1
valid_sources[0x55]	861	1			T26	13		T153	1		T28	6
valid_sources[0x56]	812	1			T4	1		T26	19		T23	4
valid_sources[0x57]	724	1			T26	16		T23	1		T152	3
valid_sources[0x58]	779	1			T45	1		T26	37		T80	3
valid_sources[0x59]	882	1			T20	1		T26	33		T152	2
valid_sources[0x5a]	543	1			T26	20		T80	1		T152	2
valid_sources[0x5b]	735	1			T26	6		T162	1		T23	2
valid_sources[0x5c]	1064	1			T26	22		T23	1		T27	2
valid_sources[0x5d]	853	1			T26	19		T118	7		T135	1
valid_sources[0x5e]	695	1			T161	1		T26	24		T152	1
valid_sources[0x5f]	613	1			T20	4		T26	14		T81	5
valid_sources[0x60]	583	1			T26	11		T23	1		T159	1
valid_sources[0x61]	860	1			T46	2		T20	2		T26	15
valid_sources[0x62]	560	1			T4	1		T20	1		T43	1
valid_sources[0x63]	955	1			T10	1		T65	1		T66	1
valid_sources[0x64]	469	1			T26	17		T152	1		T28	14
valid_sources[0x65]	741	1			T26	39		T152	3		T155	2
valid_sources[0x66]	865	1			T26	33		T23	1		T28	16
valid_sources[0x67]	584	1			T66	6		T26	41		T23	2
valid_sources[0x68]	730	1			T5	11		T26	17		T35	1
valid_sources[0x69]	735	1			T65	1		T26	18		T163	1
valid_sources[0x6a]	791	1			T65	1		T26	13		T23	1
valid_sources[0x6b]	825	1			T26	15		T135	2		T35	1
valid_sources[0x6c]	522	1			T26	12		T23	1		T152	1
valid_sources[0x6d]	888	1			T66	3		T26	6		T23	1
valid_sources[0x6e]	818	1			T22	227		T26	20		T164	1
valid_sources[0x6f]	602	1			T26	29		T153	2		T35	1
valid_sources[0x70]	660	1			T26	17		T152	1		T27	3
valid_sources[0x71]	760	1			T26	17		T23	2		T155	5
valid_sources[0x72]	544	1			T42	1		T26	16		T135	1
valid_sources[0x73]	995	1			T20	2		T26	14		T86	1
valid_sources[0x74]	946	1			T12	4		T26	19		T165	1
valid_sources[0x75]	668	1			T26	23		T23	1		T135	2
valid_sources[0x76]	710	1			T156	3		T26	27		T151	22
valid_sources[0x77]	572	1			T26	21		T152	1		T101	1
valid_sources[0x78]	811	1			T26	14		T159	1		T152	1
valid_sources[0x79]	663	1			T3	3		T26	16		T153	1
valid_sources[0x7a]	664	1			T9	2		T6	5		T26	14
valid_sources[0x7b]	910	1			T26	16		T34	1		T35	1
valid_sources[0x7c]	725	1			T26	24		T159	1		T152	1
valid_sources[0x7d]	980	1			T26	34		T23	3		T153	2
valid_sources[0x7e]	694	1			T42	1		T20	3		T26	21
valid_sources[0x7f]	690	1			T26	10		T23	1		T35	1
valid_sources[0x80]	958	1			T10	2		T117	1		T26	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44140

1

T4

4

T25

2

T5

16

values[0x0]

all_enables

biggest_size

60054

1

T2

2

T3

2

T10

1

values[0x1]

all_enables

biggest_size

58537

1

T3

1

T7

1

T10

1