Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14039936

1

T1

1921

T2

875

T3

9141

full_word

54502490

1

T1

18579

T2

8767

T3

91808

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68542096	1			T1	20500		T2	9642		T3	100949
auto[TlIntgErrCmd]	118	1			T67	8		T68	7		T69	2
auto[TlIntgErrData]	94	1			T67	7		T68	6		T69	5
auto[TlIntgErrBoth]	118	1			T67	5		T68	7		T69	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31462245

1

T1

10237

T2

4760

T3

50640

auto[1]

37080181

1

T1

10263

T2

4882

T3

50309

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6709803	1			T1	957		T2	456		T3	4679
auto[TlIntgErrNone]	partial	auto[1]	7329832	1			T1	964		T2	419		T3	4462
auto[TlIntgErrNone]	full_word	auto[0]	24752305	1			T1	9280		T2	4304		T3	45961
auto[TlIntgErrNone]	full_word	auto[1]	29750156	1			T1	9299		T2	4463		T3	45847
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T67	1		T68	1		T69	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T67	5		T68	6		T69	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T67	1		T139	1		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T67	1		T136	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T67	4		T68	2		T69	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T67	2		T68	4		T69	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T136	1		T142	1		T143	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T67	1		T136	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T67	1		T68	2		T69	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T67	3		T68	5		T69	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T67	1		T137	1		T141	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T142	1		T144	1		-	-