Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	678961	1			T2	1298		T8	19		T11	13901
auto[1]	10928256	1			T1	7119		T2	319		T3	19061
auto[2]	561906	1			T2	1264		T8	10		T11	12347
auto[3]	10821618	1			T1	7163		T2	192		T3	18731

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14881892	1			T1	11817		T2	2384		T3	31739
auto[1]	2193529	1			T1	1144		T2	342		T3	2873
auto[2]	2214580	1			T1	1192		T2	305		T3	2924
auto[3]	3700740	1			T1	129		T2	42		T3	256

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9110041

1

T1

14267

T2

3071

T3

37741

auto[1]

13880700

1

T1

15

T2

2

T3

51

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	294630	1			T2	1059		T8	14		T11	11505
auto[0]	auto[0]	auto[1]	30799	1			T2	113		T8	2		T11	1134
auto[0]	auto[0]	auto[2]	30558	1			T2	109		T8	3		T11	1140
auto[0]	auto[0]	auto[3]	9349	1			T2	16		T11	113		T25	14
auto[0]	auto[1]	auto[0]	3459647	1			T1	5886		T2	177		T3	15962
auto[0]	auto[1]	auto[1]	357478	1			T1	558		T2	111		T3	1368
auto[0]	auto[1]	auto[2]	349967	1			T1	609		T2	23		T3	1578
auto[0]	auto[1]	auto[3]	73556	1			T1	58		T2	7		T3	128
auto[0]	auto[2]	auto[0]	252182	1			T2	1053		T11	10262		T25	799
auto[0]	auto[2]	auto[1]	26277	1			T2	112		T11	1028		T25	73
auto[0]	auto[2]	auto[2]	26990	1			T2	92		T8	10		T11	935
auto[0]	auto[2]	auto[3]	7986	1			T2	7		T11	104		T25	8
auto[0]	auto[3]	auto[0]	3414995	1			T1	5922		T2	93		T3	15737
auto[0]	auto[3]	auto[1]	345437	1			T1	582		T2	6		T3	1499
auto[0]	auto[3]	auto[2]	355856	1			T1	582		T2	81		T3	1341
auto[0]	auto[3]	auto[3]	74334	1			T1	70		T2	12		T3	128
auto[1]	auto[0]	auto[0]	10594	1			T2	1		T11	8		T73	401
auto[1]	auto[0]	auto[1]	46403	1			T73	1931		T81	2664		T118	3501
auto[1]	auto[0]	auto[2]	46483	1			T11	1		T73	1846		T65	2
auto[1]	auto[0]	auto[3]	210145	1			T73	8547		T81	11888		T118	15546
auto[1]	auto[1]	auto[0]	3719293	1			T1	6		T2	1		T3	21
auto[1]	auto[1]	auto[1]	689622	1			T1	2		T3	1		T7	11725
auto[1]	auto[1]	auto[2]	683939	1			T3	3		T7	13382		T4	1
auto[1]	auto[1]	auto[3]	1594754	1			T7	53176		T11	1		T57	448
auto[1]	auto[2]	auto[0]	7015	1			T11	13		T25	1		T73	242
auto[1]	auto[2]	auto[1]	30616	1			T11	1		T73	1190		T81	2432
auto[1]	auto[2]	auto[2]	38160	1			T11	3		T73	2027		T81	1785
auto[1]	auto[2]	auto[3]	172680	1			T11	1		T73	9277		T81	8191
auto[1]	auto[3]	auto[0]	3723536	1			T1	3		T3	19		T7	2941
auto[1]	auto[3]	auto[1]	666897	1			T1	2		T3	5		T7	13097
auto[1]	auto[3]	auto[2]	682627	1			T1	1		T3	2		T7	11775
auto[1]	auto[3]	auto[3]	1557936	1			T1	1		T7	53414		T21	1