Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	304960338	251285	0	0
ctrl_regwen_rd_A	304960338	4186	0	0
exec_rd_A	304960338	3837	0	0
exec_regwen_rd_A	304960338	4298	0	0
readback_rd_A	304960338	2685	0	0
readback_regwen_rd_A	304960338	2166	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304960338	251285	0	0
T26	162561	7437	0	0
T27	0	1732	0	0
T28	0	4225	0	0
T31	3021	0	0	0
T47	0	6877	0	0
T55	44328	0	0	0
T61	0	6312	0	0
T74	0	4869	0	0
T75	0	4800	0	0
T76	0	6485	0	0
T77	0	3987	0	0
T78	0	6055	0	0
T79	440399	0	0	0
T80	453364	0	0	0
T81	121545	0	0	0
T82	527174	0	0	0
T83	7123	0	0	0
T84	7765	0	0	0
T85	126844	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304960338	4186	0	0
T27	37547	93	0	0
T28	0	138	0	0
T47	0	412	0	0
T52	9904	0	0	0
T56	9070	0	0	0
T74	0	413	0	0
T76	0	229	0	0
T123	0	189	0	0
T124	0	256	0	0
T125	0	321	0	0
T126	0	93	0	0
T127	0	155	0	0
T128	109503	0	0	0
T129	1160	0	0	0
T130	9923	0	0	0
T131	186307	0	0	0
T132	633	0	0	0
T133	239699	0	0	0
T134	153581	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304960338	3837	0	0
T27	37547	95	0	0
T28	0	140	0	0
T47	0	458	0	0
T52	9904	0	0	0
T56	9070	0	0	0
T74	0	275	0	0
T76	0	218	0	0
T123	0	175	0	0
T124	0	290	0	0
T125	0	322	0	0
T126	0	74	0	0
T127	0	98	0	0
T128	109503	0	0	0
T129	1160	0	0	0
T130	9923	0	0	0
T131	186307	0	0	0
T132	633	0	0	0
T133	239699	0	0	0
T134	153581	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304960338	4298	0	0
T27	37547	188	0	0
T28	0	155	0	0
T47	0	562	0	0
T52	9904	0	0	0
T56	9070	0	0	0
T74	0	309	0	0
T76	0	179	0	0
T123	0	141	0	0
T124	0	283	0	0
T125	0	353	0	0
T126	0	65	0	0
T127	0	134	0	0
T128	109503	0	0	0
T129	1160	0	0	0
T130	9923	0	0	0
T131	186307	0	0	0
T132	633	0	0	0
T133	239699	0	0	0
T134	153581	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304960338	2685	0	0
T27	37547	105	0	0
T28	0	168	0	0
T47	0	502	0	0
T52	9904	0	0	0
T56	9070	0	0	0
T74	0	326	0	0
T76	0	172	0	0
T123	0	148	0	0
T124	0	252	0	0
T125	0	414	0	0
T126	0	68	0	0
T127	0	120	0	0
T128	109503	0	0	0
T129	1160	0	0	0
T130	9923	0	0	0
T131	186307	0	0	0
T132	633	0	0	0
T133	239699	0	0	0
T134	153581	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304960338	2166	0	0
T27	37547	35	0	0
T28	0	103	0	0
T47	0	395	0	0
T52	9904	0	0	0
T56	9070	0	0	0
T74	0	257	0	0
T76	0	142	0	0
T123	0	173	0	0
T124	0	243	0	0
T125	0	301	0	0
T126	0	64	0	0
T127	0	128	0	0
T128	109503	0	0	0
T129	1160	0	0	0
T130	9923	0	0	0
T131	186307	0	0	0
T132	633	0	0	0
T133	239699	0	0	0
T134	153581	0	0	0