Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14026226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58886699

1

T1

1677

T2

9768

T4

103699

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36357114	1			T1	940		T2	4884		T4	56881
values[0x0]	16874704	1			T1	435		T2	2415		T4	27638
values[0x1]	19681107	1			T1	468		T2	2469		T4	29419

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6986967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65925958

1

T1

1761

T2

9768

T4

108783

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	288859	1			T1	4		T2	59		T4	325
valid_sources[0x01]	325239	1			T1	8		T2	43		T4	257
valid_sources[0x02]	314086	1			T1	5		T2	46		T4	419
valid_sources[0x03]	260044	1			T1	5		T2	35		T4	469
valid_sources[0x04]	309790	1			T1	25		T2	35		T4	593
valid_sources[0x05]	257426	1			T1	4		T2	31		T4	426
valid_sources[0x06]	298612	1			T1	8		T2	46		T4	411
valid_sources[0x07]	244479	1			T1	1		T2	36		T4	410
valid_sources[0x08]	256491	1			T1	1		T2	24		T4	318
valid_sources[0x09]	243944	1			T1	7		T2	31		T4	298
valid_sources[0x0a]	288415	1			T1	8		T2	42		T4	549
valid_sources[0x0b]	255255	1			T2	40		T4	417		T5	1032
valid_sources[0x0c]	304072	1			T2	52		T4	454		T5	1042
valid_sources[0x0d]	262178	1			T1	4		T2	41		T4	541
valid_sources[0x0e]	265088	1			T1	11		T2	38		T4	419
valid_sources[0x0f]	254941	1			T1	1		T2	31		T4	462
valid_sources[0x10]	260103	1			T1	7		T2	42		T4	341
valid_sources[0x11]	285456	1			T1	1		T2	38		T4	621
valid_sources[0x12]	295748	1			T2	34		T4	348		T5	1116
valid_sources[0x13]	289818	1			T1	13		T2	52		T4	434
valid_sources[0x14]	296639	1			T1	6		T2	55		T4	441
valid_sources[0x15]	380592	1			T1	6		T2	44		T4	483
valid_sources[0x16]	256375	1			T1	14		T2	26		T4	318
valid_sources[0x17]	415950	1			T1	4		T2	29		T4	633
valid_sources[0x18]	280435	1			T2	35		T4	422		T5	1061
valid_sources[0x19]	335148	1			T1	26		T2	39		T4	472
valid_sources[0x1a]	312498	1			T1	6		T2	47		T4	390
valid_sources[0x1b]	292459	1			T1	16		T2	42		T4	431
valid_sources[0x1c]	248116	1			T1	4		T2	38		T4	481
valid_sources[0x1d]	408774	1			T1	8		T2	46		T4	366
valid_sources[0x1e]	265555	1			T1	10		T2	29		T4	430
valid_sources[0x1f]	267105	1			T1	12		T2	42		T4	478
valid_sources[0x20]	312428	1			T1	22		T2	38		T4	481
valid_sources[0x21]	327285	1			T1	2		T2	44		T4	446
valid_sources[0x22]	285046	1			T1	9		T2	42		T4	351
valid_sources[0x23]	254296	1			T1	11		T2	46		T4	402
valid_sources[0x24]	250909	1			T2	33		T4	330		T5	1022
valid_sources[0x25]	257332	1			T1	23		T2	27		T4	491
valid_sources[0x26]	267208	1			T2	29		T4	526		T5	1090
valid_sources[0x27]	288677	1			T2	20		T4	370		T5	1009
valid_sources[0x28]	251195	1			T1	6		T2	19		T4	489
valid_sources[0x29]	244834	1			T1	12		T2	28		T4	568
valid_sources[0x2a]	344722	1			T1	8		T2	40		T4	264
valid_sources[0x2b]	259391	1			T1	2		T2	41		T4	538
valid_sources[0x2c]	258467	1			T1	3		T2	34		T4	551
valid_sources[0x2d]	265617	1			T1	9		T2	34		T4	448
valid_sources[0x2e]	276216	1			T1	5		T2	36		T4	412
valid_sources[0x2f]	312946	1			T1	8		T2	27		T4	513
valid_sources[0x30]	281507	1			T1	1		T2	49		T4	353
valid_sources[0x31]	285929	1			T1	5		T2	46		T4	365
valid_sources[0x32]	263753	1			T2	39		T4	338		T5	999
valid_sources[0x33]	246962	1			T2	48		T4	427		T5	990
valid_sources[0x34]	263520	1			T1	5		T2	28		T4	376
valid_sources[0x35]	343560	1			T1	8		T2	38		T4	313
valid_sources[0x36]	241296	1			T1	7		T2	30		T4	469
valid_sources[0x37]	364551	1			T1	14		T2	42		T4	522
valid_sources[0x38]	259166	1			T1	10		T2	33		T4	441
valid_sources[0x39]	291334	1			T1	7		T2	43		T4	474
valid_sources[0x3a]	276530	1			T1	15		T2	38		T4	421
valid_sources[0x3b]	255755	1			T1	5		T2	45		T4	348
valid_sources[0x3c]	275076	1			T1	29		T2	29		T4	395
valid_sources[0x3d]	257519	1			T1	8		T2	37		T4	503
valid_sources[0x3e]	305584	1			T1	18		T2	25		T4	444
valid_sources[0x3f]	261417	1			T1	5		T2	31		T4	419
valid_sources[0x40]	305923	1			T2	44		T4	475		T5	1015
valid_sources[0x41]	257805	1			T1	3		T2	29		T4	541
valid_sources[0x42]	302834	1			T1	5		T2	32		T4	672
valid_sources[0x43]	293451	1			T1	2		T2	32		T4	421
valid_sources[0x44]	279131	1			T1	11		T2	37		T4	640
valid_sources[0x45]	281694	1			T1	9		T2	30		T4	494
valid_sources[0x46]	300611	1			T1	4		T2	24		T4	449
valid_sources[0x47]	257374	1			T1	20		T2	54		T4	601
valid_sources[0x48]	272917	1			T1	3		T2	46		T4	475
valid_sources[0x49]	274646	1			T1	9		T2	37		T4	296
valid_sources[0x4a]	295972	1			T1	6		T2	24		T4	527
valid_sources[0x4b]	345694	1			T1	2		T2	58		T4	336
valid_sources[0x4c]	244816	1			T1	2		T2	16		T4	426
valid_sources[0x4d]	283243	1			T2	34		T4	483		T5	1089
valid_sources[0x4e]	270026	1			T1	31		T2	39		T4	427
valid_sources[0x4f]	286920	1			T1	3		T2	49		T4	490
valid_sources[0x50]	282938	1			T1	16		T2	31		T4	497
valid_sources[0x51]	258992	1			T1	2		T2	34		T4	244
valid_sources[0x52]	261641	1			T1	3		T2	35		T4	313
valid_sources[0x53]	285743	1			T1	7		T2	48		T4	521
valid_sources[0x54]	248840	1			T1	6		T2	33		T4	438
valid_sources[0x55]	252658	1			T1	3		T2	51		T4	491
valid_sources[0x56]	283580	1			T1	18		T2	27		T4	507
valid_sources[0x57]	278733	1			T1	21		T2	57		T4	628
valid_sources[0x58]	385628	1			T1	6		T2	27		T4	328
valid_sources[0x59]	252803	1			T1	11		T2	36		T4	365
valid_sources[0x5a]	310311	1			T1	15		T2	34		T4	376
valid_sources[0x5b]	361191	1			T2	44		T4	564		T5	1020
valid_sources[0x5c]	271026	1			T1	4		T2	42		T4	322
valid_sources[0x5d]	311462	1			T2	40		T4	454		T5	1102
valid_sources[0x5e]	276458	1			T2	40		T4	455		T5	1025
valid_sources[0x5f]	248182	1			T1	42		T2	43		T4	460
valid_sources[0x60]	328572	1			T1	3		T2	21		T4	544
valid_sources[0x61]	260250	1			T1	23		T2	35		T4	513
valid_sources[0x62]	255480	1			T1	2		T2	33		T4	406
valid_sources[0x63]	268695	1			T1	1		T2	26		T4	530
valid_sources[0x64]	275699	1			T2	44		T4	468		T5	995
valid_sources[0x65]	314905	1			T1	8		T2	24		T4	554
valid_sources[0x66]	326796	1			T2	41		T4	481		T5	1010
valid_sources[0x67]	269475	1			T1	12		T2	38		T4	346
valid_sources[0x68]	278222	1			T1	4		T2	32		T4	351
valid_sources[0x69]	373486	1			T1	5		T2	55		T4	468
valid_sources[0x6a]	272171	1			T1	17		T2	47		T4	434
valid_sources[0x6b]	357140	1			T1	5		T2	47		T4	477
valid_sources[0x6c]	301322	1			T1	1		T2	36		T4	507
valid_sources[0x6d]	392274	1			T1	17		T2	37		T4	320
valid_sources[0x6e]	255046	1			T1	12		T2	52		T4	451
valid_sources[0x6f]	258532	1			T1	10		T2	38		T4	380
valid_sources[0x70]	315348	1			T2	33		T4	248		T5	1096
valid_sources[0x71]	270505	1			T1	3		T2	54		T4	486
valid_sources[0x72]	251803	1			T1	7		T2	36		T4	387
valid_sources[0x73]	360543	1			T1	8		T2	37		T4	432
valid_sources[0x74]	259373	1			T1	35		T2	26		T4	429
valid_sources[0x75]	268058	1			T2	31		T4	356		T5	992
valid_sources[0x76]	244107	1			T1	1		T2	17		T4	317
valid_sources[0x77]	293267	1			T1	16		T2	26		T4	403
valid_sources[0x78]	305101	1			T1	3		T2	26		T4	354
valid_sources[0x79]	281020	1			T2	26		T4	488		T5	1075
valid_sources[0x7a]	320540	1			T1	17		T2	40		T4	507
valid_sources[0x7b]	276914	1			T2	25		T4	388		T5	1112
valid_sources[0x7c]	292072	1			T1	2		T2	33		T4	410
valid_sources[0x7d]	289261	1			T1	5		T2	40		T4	472
valid_sources[0x7e]	269531	1			T1	18		T2	33		T4	411
valid_sources[0x7f]	266717	1			T1	22		T2	33		T4	360
valid_sources[0x80]	307098	1			T2	44		T4	619		T5	1064

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29350942

1

T1

856

T2

4884

T4

51799

values[0x0]

all_enables

biggest_size

14769047

1

T1

409

T2

2415

T4

26065

values[0x1]

all_enables

biggest_size

14766710

1

T1

412

T2

2469

T4

25835

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114333

1

T1

11

T2

1

T5

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43404	1			T1	16		T12	946		T18	7
values[0x0]	50346	1			T1	8		T2	2		T3	1
values[0x1]	54583	1			T1	12		T4	2		T5	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

122234

1

T1

13

T2

1

T5

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	471	1			T12	27		T21	4		T43	10
valid_sources[0x01]	436	1			T12	9		T47	5		T21	6
valid_sources[0x02]	883	1			T5	1		T12	14		T43	3
valid_sources[0x03]	565	1			T5	1		T12	22		T18	1
valid_sources[0x04]	383	1			T12	20		T21	1		T43	4
valid_sources[0x05]	559	1			T12	20		T43	2		T52	6
valid_sources[0x06]	589	1			T12	15		T21	1		T43	4
valid_sources[0x07]	700	1			T12	18		T21	272		T43	9
valid_sources[0x08]	687	1			T12	22		T19	1		T43	2
valid_sources[0x09]	537	1			T12	24		T21	143		T43	2
valid_sources[0x0a]	398	1			T12	10		T21	2		T43	5
valid_sources[0x0b]	556	1			T12	10		T19	21		T21	2
valid_sources[0x0c]	557	1			T12	19		T19	1		T21	126
valid_sources[0x0d]	670	1			T12	13		T6	1		T21	2
valid_sources[0x0e]	599	1			T12	13		T36	1		T45	1
valid_sources[0x0f]	573	1			T5	2		T12	14		T21	4
valid_sources[0x10]	780	1			T12	16		T18	1		T19	6
valid_sources[0x11]	515	1			T5	1		T12	20		T19	5
valid_sources[0x12]	464	1			T12	16		T6	1		T48	3
valid_sources[0x13]	534	1			T12	18		T6	1		T45	1
valid_sources[0x14]	546	1			T5	3		T12	9		T79	1
valid_sources[0x15]	660	1			T12	16		T19	10		T21	186
valid_sources[0x16]	479	1			T12	9		T21	5		T43	6
valid_sources[0x17]	791	1			T12	17		T21	290		T43	6
valid_sources[0x18]	410	1			T4	1		T12	13		T43	2
valid_sources[0x19]	589	1			T12	15		T19	1		T21	1
valid_sources[0x1a]	372	1			T12	6		T19	1		T21	2
valid_sources[0x1b]	485	1			T12	12		T19	1		T21	37
valid_sources[0x1c]	779	1			T12	9		T43	6		T52	22
valid_sources[0x1d]	539	1			T12	9		T19	64		T21	48
valid_sources[0x1e]	448	1			T12	17		T46	2		T19	1
valid_sources[0x1f]	575	1			T12	17		T21	111		T43	2
valid_sources[0x20]	378	1			T12	7		T43	4		T141	2
valid_sources[0x21]	693	1			T12	14		T6	1		T22	1
valid_sources[0x22]	529	1			T9	1		T12	16		T18	2
valid_sources[0x23]	408	1			T12	9		T43	4		T142	1
valid_sources[0x24]	405	1			T12	15		T43	3		T143	1
valid_sources[0x25]	820	1			T11	1		T12	5		T21	1
valid_sources[0x26]	516	1			T12	20		T7	8		T43	4
valid_sources[0x27]	544	1			T12	14		T21	131		T43	1
valid_sources[0x28]	357	1			T5	2		T12	9		T52	10
valid_sources[0x29]	1107	1			T12	10		T21	90		T43	1
valid_sources[0x2a]	528	1			T12	9		T6	2		T21	1
valid_sources[0x2b]	431	1			T12	21		T21	56		T119	1
valid_sources[0x2c]	522	1			T12	13		T43	2		T20	2
valid_sources[0x2d]	682	1			T12	6		T19	1		T21	1
valid_sources[0x2e]	522	1			T12	12		T43	2		T63	8
valid_sources[0x2f]	559	1			T12	17		T18	2		T19	1
valid_sources[0x30]	567	1			T12	8		T6	1		T19	1
valid_sources[0x31]	830	1			T12	16		T19	197		T52	27
valid_sources[0x32]	332	1			T5	2		T12	22		T19	9
valid_sources[0x33]	576	1			T12	23		T19	1		T21	7
valid_sources[0x34]	638	1			T12	13		T6	1		T19	144
valid_sources[0x35]	548	1			T12	7		T43	7		T52	1
valid_sources[0x36]	719	1			T8	1		T12	21		T6	1
valid_sources[0x37]	399	1			T12	11		T18	1		T43	8
valid_sources[0x38]	396	1			T12	15		T6	1		T21	3
valid_sources[0x39]	786	1			T12	21		T18	1		T144	1
valid_sources[0x3a]	359	1			T12	13		T19	5		T23	1
valid_sources[0x3b]	567	1			T12	17		T21	174		T13	1
valid_sources[0x3c]	624	1			T12	14		T6	1		T43	3
valid_sources[0x3d]	610	1			T12	7		T21	167		T62	9
valid_sources[0x3e]	504	1			T12	37		T21	103		T43	10
valid_sources[0x3f]	344	1			T12	18		T21	1		T43	2
valid_sources[0x40]	503	1			T12	19		T43	2		T89	1
valid_sources[0x41]	452	1			T11	2		T12	12		T18	2
valid_sources[0x42]	751	1			T12	19		T6	1		T21	2
valid_sources[0x43]	651	1			T12	9		T19	4		T21	295
valid_sources[0x44]	755	1			T12	12		T21	5		T43	5
valid_sources[0x45]	412	1			T12	10		T18	1		T19	1
valid_sources[0x46]	614	1			T12	13		T21	243		T43	4
valid_sources[0x47]	738	1			T12	15		T43	6		T141	1
valid_sources[0x48]	401	1			T5	1		T12	25		T6	1
valid_sources[0x49]	649	1			T12	19		T43	4		T145	1
valid_sources[0x4a]	938	1			T2	2		T11	1		T12	19
valid_sources[0x4b]	454	1			T11	1		T12	26		T43	20
valid_sources[0x4c]	658	1			T12	22		T21	17		T43	4
valid_sources[0x4d]	404	1			T12	11		T21	5		T43	9
valid_sources[0x4e]	559	1			T12	28		T18	1		T19	2
valid_sources[0x4f]	711	1			T11	1		T12	16		T21	3
valid_sources[0x50]	732	1			T12	14		T19	2		T21	52
valid_sources[0x51]	399	1			T12	6		T18	1		T43	7
valid_sources[0x52]	501	1			T5	2		T12	6		T43	3
valid_sources[0x53]	593	1			T12	11		T19	219		T21	2
valid_sources[0x54]	919	1			T12	21		T19	154		T21	61
valid_sources[0x55]	762	1			T5	1		T12	10		T43	1
valid_sources[0x56]	416	1			T11	1		T12	15		T6	2
valid_sources[0x57]	697	1			T12	20		T21	2		T43	4
valid_sources[0x58]	655	1			T12	14		T6	2		T43	5
valid_sources[0x59]	392	1			T12	12		T43	2		T120	1
valid_sources[0x5a]	480	1			T12	16		T21	1		T43	3
valid_sources[0x5b]	582	1			T12	10		T43	1		T52	26
valid_sources[0x5c]	802	1			T12	14		T6	2		T19	1
valid_sources[0x5d]	427	1			T12	7		T19	2		T21	11
valid_sources[0x5e]	412	1			T12	9		T145	1		T52	10
valid_sources[0x5f]	595	1			T12	13		T43	5		T146	1
valid_sources[0x60]	414	1			T12	14		T6	1		T43	1
valid_sources[0x61]	422	1			T5	1		T12	11		T19	3
valid_sources[0x62]	458	1			T12	17		T54	1		T120	1
valid_sources[0x63]	407	1			T9	1		T12	26		T19	3
valid_sources[0x64]	532	1			T9	1		T12	28		T21	3
valid_sources[0x65]	623	1			T12	15		T43	8		T52	14
valid_sources[0x66]	490	1			T12	17		T19	63		T21	1
valid_sources[0x67]	704	1			T12	7		T19	3		T43	9
valid_sources[0x68]	643	1			T5	1		T12	16		T6	1
valid_sources[0x69]	822	1			T5	1		T12	8		T18	1
valid_sources[0x6a]	768	1			T12	16		T18	1		T21	4
valid_sources[0x6b]	586	1			T12	9		T19	84		T21	1
valid_sources[0x6c]	802	1			T12	6		T19	2		T62	1
valid_sources[0x6d]	492	1			T12	18		T19	7		T79	1
valid_sources[0x6e]	628	1			T12	15		T36	1		T21	74
valid_sources[0x6f]	685	1			T5	1		T12	10		T20	2
valid_sources[0x70]	654	1			T12	7		T59	119		T21	1
valid_sources[0x71]	585	1			T12	12		T43	8		T145	1
valid_sources[0x72]	642	1			T12	8		T21	59		T43	8
valid_sources[0x73]	478	1			T12	12		T21	1		T147	2
valid_sources[0x74]	600	1			T12	10		T18	1		T21	23
valid_sources[0x75]	709	1			T5	1		T12	20		T19	48
valid_sources[0x76]	585	1			T5	2		T12	19		T21	3
valid_sources[0x77]	675	1			T10	3		T12	9		T19	166
valid_sources[0x78]	417	1			T12	14		T6	1		T107	4
valid_sources[0x79]	521	1			T12	16		T38	35		T43	5
valid_sources[0x7a]	481	1			T11	1		T12	12		T21	112
valid_sources[0x7b]	726	1			T12	18		T19	1		T110	2
valid_sources[0x7c]	537	1			T5	1		T12	12		T6	1
valid_sources[0x7d]	717	1			T12	10		T21	195		T43	3
valid_sources[0x7e]	379	1			T9	1		T12	14		T43	2
valid_sources[0x7f]	500	1			T12	8		T43	8		T20	1
valid_sources[0x80]	916	1			T12	16		T21	5		T43	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31567

1

T1

8

T12

883

T18

3

values[0x0]

all_enables

biggest_size

42085

1

T1

2

T2

1

T5

10

values[0x1]

all_enables

biggest_size

40681

1

T1

1

T5

3

T8

1