Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13687986

1

T1

50

T4

10239

T5

19621

full_word

53969300

1

T1

408

T2

9768

T4

103699

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67657006	1			T1	458		T2	9768		T4	113938
auto[TlIntgErrCmd]	93	1			T56	1		T57	4		T58	3
auto[TlIntgErrData]	82	1			T56	4		T57	2		T58	3
auto[TlIntgErrBoth]	105	1			T56	5		T57	4		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31058872

1

T1

252

T2

4884

T4

56881

auto[1]

36598414

1

T1

206

T2

4884

T4

57057

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6552149	1			T1	27		T4	5082		T5	7288
auto[TlIntgErrNone]	partial	auto[1]	7135577	1			T1	23		T4	5157		T5	12333
auto[TlIntgErrNone]	full_word	auto[0]	24506600	1			T1	225		T2	4884		T4	51799
auto[TlIntgErrNone]	full_word	auto[1]	29462680	1			T1	183		T2	4884		T4	51900
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T58	1		T124	3		T125	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T56	1		T57	4		T58	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T124	1		T126	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T56	2		T58	1		T124	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T56	1		T57	2		T58	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T56	1		T125	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T129	1		T130	2		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T56	2		T57	3		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T56	3		T57	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T131	1		T132	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T125	1		T134	1		T132	2