Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	682998	1			T5	32		T11	11		T12	2028
auto[1]	10312832	1			T1	221		T2	4881		T4	47610
auto[2]	558795	1			T5	29		T11	15		T12	1839
auto[3]	10197442	1			T1	180		T2	4883		T4	47500

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14336146	1			T1	319		T2	9764		T4	79428
auto[1]	2052313	1			T1	36		T4	7535		T5	117
auto[2]	2066165	1			T1	39		T4	7424		T5	167
auto[3]	3297443	1			T1	7		T4	723		T5	22

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8714153

1

T1

401

T2

9748

T4

19

auto[1]

13037914

1

T2

16

T4

95091

T5

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	225206	1			T5	24		T11	10		T12	1649
auto[0]	auto[0]	auto[1]	23775	1			T5	3		T12	186		T18	95
auto[0]	auto[0]	auto[2]	23545	1			T5	4		T11	1		T12	176
auto[0]	auto[0]	auto[3]	9077	1			T12	14		T18	13		T107	2
auto[0]	auto[1]	auto[0]	3356307	1			T1	178		T2	4874		T4	10
auto[0]	auto[1]	auto[1]	346677	1			T1	17		T5	71		T11	59
auto[0]	auto[1]	auto[2]	337192	1			T1	20		T5	35		T11	25
auto[0]	auto[1]	auto[3]	70538	1			T1	6		T4	1		T5	9
auto[0]	auto[2]	auto[0]	193083	1			T12	1532		T18	925		T6	13
auto[0]	auto[2]	auto[1]	20329	1			T12	157		T18	90		T6	1
auto[0]	auto[2]	auto[2]	22593	1			T5	26		T11	12		T12	135
auto[0]	auto[2]	auto[3]	7696	1			T5	3		T11	3		T12	10
auto[0]	auto[3]	auto[0]	3325863	1			T1	141		T2	4874		T4	7
auto[0]	auto[3]	auto[1]	334785	1			T1	19		T5	41		T11	29
auto[0]	auto[3]	auto[2]	345961	1			T1	19		T4	1		T5	102
auto[0]	auto[3]	auto[3]	71526	1			T1	1		T5	10		T11	13
auto[1]	auto[0]	auto[0]	13571	1			T5	1		T12	3		T18	3
auto[1]	auto[0]	auto[1]	59513	1			T107	4147		T108	973		T110	744
auto[1]	auto[0]	auto[2]	59656	1			T107	4097		T108	928		T110	746
auto[1]	auto[0]	auto[3]	268655	1			T107	18879		T108	4263		T110	3406
auto[1]	auto[1]	auto[0]	3609295	1			T2	7		T4	39725		T5	1
auto[1]	auto[1]	auto[1]	631863	1			T4	3599		T5	2		T9	6130
auto[1]	auto[1]	auto[2]	608633	1			T4	3914		T9	5759		T35	1
auto[1]	auto[1]	auto[3]	1352327	1			T4	361		T9	602		T79	884
auto[1]	auto[2]	auto[0]	9684	1			T12	3		T107	841		T108	109
auto[1]	auto[2]	auto[1]	42323	1			T12	2		T107	3984		T108	575
auto[1]	auto[2]	auto[2]	47755	1			T107	3470		T108	945		T110	650
auto[1]	auto[2]	auto[3]	215332	1			T107	15706		T108	4028		T110	3045
auto[1]	auto[3]	auto[0]	3603137	1			T2	9		T4	39686		T5	1
auto[1]	auto[3]	auto[1]	593048	1			T4	3936		T9	6015		T37	1
auto[1]	auto[3]	auto[2]	620830	1			T4	3509		T9	5900		T79	8753
auto[1]	auto[3]	auto[3]	1302292	1			T4	361		T9	582		T79	846