Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	310330809	163813	0	0
ctrl_regwen_rd_A	310330809	2742	0	0
exec_rd_A	310330809	2545	0	0
exec_regwen_rd_A	310330809	2593	0	0
readback_rd_A	310330809	1356	0	0
readback_regwen_rd_A	310330809	1197	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310330809	163813	0	0
T6	50467	0	0	0
T12	286367	4798	0	0
T18	816665	0	0	0
T19	0	4148	0	0
T21	0	10535	0	0
T35	10436	0	0	0
T36	10378	0	0	0
T37	5173	0	0	0
T43	0	525	0	0
T46	3623	0	0	0
T49	18987	0	0	0
T52	0	4632	0	0
T54	13089	0	0	0
T55	6111	0	0	0
T63	0	4307	0	0
T64	0	2901	0	0
T65	0	3947	0	0
T66	0	3766	0	0
T67	0	5381	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310330809	2742	0	0
T13	1061	0	0	0
T14	819	0	0	0
T41	0	340	0	0
T42	0	113	0	0
T43	14421	62	0	0
T44	12501	0	0	0
T48	8854	0	0	0
T50	10867	0	0	0
T112	0	297	0	0
T113	0	230	0	0
T114	0	116	0	0
T115	0	137	0	0
T116	0	97	0	0
T117	0	15	0	0
T118	0	44	0	0
T119	12725	0	0	0
T120	366041	0	0	0
T121	13154	0	0	0
T122	2757	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310330809	2545	0	0
T13	1061	0	0	0
T14	819	0	0	0
T41	0	307	0	0
T42	0	115	0	0
T43	14421	102	0	0
T44	12501	0	0	0
T48	8854	0	0	0
T50	10867	0	0	0
T60	0	6	0	0
T112	0	281	0	0
T113	0	198	0	0
T114	0	57	0	0
T115	0	100	0	0
T116	0	104	0	0
T117	0	33	0	0
T119	12725	0	0	0
T120	366041	0	0	0
T121	13154	0	0	0
T122	2757	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310330809	2593	0	0
T13	1061	0	0	0
T14	819	0	0	0
T41	0	279	0	0
T42	0	124	0	0
T43	14421	68	0	0
T44	12501	0	0	0
T48	8854	0	0	0
T50	10867	0	0	0
T112	0	337	0	0
T113	0	170	0	0
T114	0	46	0	0
T115	0	108	0	0
T116	0	105	0	0
T117	0	36	0	0
T118	0	34	0	0
T119	12725	0	0	0
T120	366041	0	0	0
T121	13154	0	0	0
T122	2757	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310330809	1356	0	0
T13	1061	0	0	0
T14	819	0	0	0
T41	0	316	0	0
T42	0	70	0	0
T43	14421	36	0	0
T44	12501	0	0	0
T48	8854	0	0	0
T50	10867	0	0	0
T112	0	284	0	0
T113	0	199	0	0
T114	0	57	0	0
T115	0	73	0	0
T116	0	89	0	0
T117	0	16	0	0
T118	0	65	0	0
T119	12725	0	0	0
T120	366041	0	0	0
T121	13154	0	0	0
T122	2757	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310330809	1197	0	0
T13	1061	0	0	0
T14	819	0	0	0
T41	0	246	0	0
T42	0	83	0	0
T43	14421	39	0	0
T44	12501	0	0	0
T48	8854	0	0	0
T50	10867	0	0	0
T112	0	216	0	0
T113	0	165	0	0
T114	0	46	0	0
T115	0	99	0	0
T116	0	134	0	0
T117	0	23	0	0
T118	0	30	0	0
T119	12725	0	0	0
T120	366041	0	0	0
T121	13154	0	0	0
T122	2757	0	0	0