Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13541077

1

T2

8200

T3

26

T5

1691

full_word

55408953

1

T1

3071

T2

1846

T3

265

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68949750	1			T1	3071		T2	10046		T3	291
auto[TlIntgErrCmd]	93	1			T64	3		T65	2		T66	4
auto[TlIntgErrData]	91	1			T64	8		T65	7		T66	5
auto[TlIntgErrBoth]	96	1			T64	9		T65	1		T66	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31280361

1

T1

1024

T2

5051

T3

155

auto[1]

37669669

1

T1

2047

T2

4995

T3

136

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6436762	1			T2	4118		T3	11		T5	889
auto[TlIntgErrNone]	partial	auto[1]	7104057	1			T2	4082		T3	15		T5	802
auto[TlIntgErrNone]	full_word	auto[0]	24843485	1			T1	1024		T2	933		T3	144
auto[TlIntgErrNone]	full_word	auto[1]	30565446	1			T1	2047		T2	913		T3	121
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T119	1		T120	3		T125	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T64	3		T65	2		T66	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T122	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T119	1		T126	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T64	3		T65	2		T66	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T64	3		T65	5		T66	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T64	1		T125	2		T121	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T64	1		T119	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T64	2		T120	3		T125	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T64	6		T65	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T64	1		T119	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T66	1		T125	1		T128	1