Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	733633	1			T2	1342		T6	20		T7	5
auto[1]	10162408	1			T2	1118		T3	135		T5	4767
auto[2]	617471	1			T2	904		T6	17		T7	5
auto[3]	10057260	1			T2	780		T3	126		T5	4673

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14036982	1			T2	90		T3	204		T5	6420
auto[1]	2050661	1			T2	590		T3	32		T5	1329
auto[2]	2067316	1			T2	516		T3	23		T5	1415
auto[3]	3415813	1			T2	2948		T3	2		T5	276

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8547610

1

T2

4134

T3

261

T5

9433

auto[1]

13023162

1

T2

10

T5

7

T10

43

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	294923	1			T2	50		T6	16		T7	4
auto[0]	auto[0]	auto[1]	31038	1			T2	215		T6	1		T41	215
auto[0]	auto[0]	auto[2]	30901	1			T2	207		T6	3		T7	1
auto[0]	auto[0]	auto[3]	9375	1			T2	867		T41	27		T25	55
auto[0]	auto[1]	auto[0]	3227521	1			T2	5		T3	105		T5	3211
auto[0]	auto[1]	auto[1]	337022	1			T2	192		T3	19		T5	664
auto[0]	auto[1]	auto[2]	323491	1			T2	32		T3	10		T5	750
auto[0]	auto[1]	auto[3]	67340	1			T2	885		T3	1		T5	139
auto[0]	auto[2]	auto[0]	254852	1			T2	31		T6	15		T7	4
auto[0]	auto[2]	auto[1]	26354	1			T2	169		T6	1		T7	1
auto[0]	auto[2]	auto[2]	27317	1			T2	132		T6	1		T41	248
auto[0]	auto[2]	auto[3]	7839	1			T2	571		T41	24		T25	35
auto[0]	auto[3]	auto[0]	3187977	1			T2	3		T3	99		T5	3203
auto[0]	auto[3]	auto[1]	320112	1			T2	13		T3	13		T5	664
auto[0]	auto[3]	auto[2]	333604	1			T2	145		T3	13		T5	665
auto[0]	auto[3]	auto[3]	67944	1			T2	617		T3	1		T5	137
auto[1]	auto[0]	auto[0]	12507	1			T134	1		T46	5		T135	1
auto[1]	auto[0]	auto[1]	54375	1			T41	1		T46	2		T131	3108
auto[1]	auto[0]	auto[2]	54675	1			T46	1		T131	3109		T132	495
auto[1]	auto[0]	auto[3]	245839	1			T2	3		T131	13816		T132	2160
auto[1]	auto[1]	auto[0]	3524584	1			T5	2		T10	19		T63	3
auto[1]	auto[1]	auto[1]	643213	1			T2	1		T5	1		T67	9198
auto[1]	auto[1]	auto[2]	617465	1			T67	9080		T100	15012		T101	5656
auto[1]	auto[1]	auto[3]	1421772	1			T2	3		T10	1		T67	959
auto[1]	auto[2]	auto[0]	8841	1			T2	1		T41	4		T45	1
auto[1]	auto[2]	auto[1]	38167	1			T41	1		T131	2828		T136	1
auto[1]	auto[2]	auto[2]	46097	1			T131	2067		T132	431		T133	559
auto[1]	auto[2]	auto[3]	208004	1			T131	9401		T132	1961		T133	2361
auto[1]	auto[3]	auto[0]	3525777	1			T5	4		T10	19		T63	1
auto[1]	auto[3]	auto[1]	600380	1			T10	2		T63	2		T67	9072
auto[1]	auto[3]	auto[2]	633766	1			T10	2		T67	9125		T100	14693
auto[1]	auto[3]	auto[3]	1387700	1			T2	2		T67	906		T100	67548