Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	316587867	217546	0	0
ctrl_regwen_rd_A	316587867	3998	0	0
exec_rd_A	316587867	3560	0	0
exec_regwen_rd_A	316587867	4079	0	0
readback_rd_A	316587867	2615	0	0
readback_regwen_rd_A	316587867	2143	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316587867	217546	0	0
T6	48714	0	0	0
T7	10873	0	0	0
T11	175738	6716	0	0
T20	0	8950	0	0
T24	26113	0	0	0
T25	17964	0	0	0
T26	0	4769	0	0
T28	2639	0	0	0
T41	203315	0	0	0
T47	65720	0	0	0
T54	51609	0	0	0
T56	0	4882	0	0
T58	0	6868	0	0
T59	0	7976	0	0
T60	0	1746	0	0
T62	0	3896	0	0
T63	10620	0	0	0
T70	0	4832	0	0
T71	0	3861	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316587867	3998	0	0
T6	48714	0	0	0
T7	10873	0	0	0
T11	175738	260	0	0
T24	26113	0	0	0
T25	17964	0	0	0
T28	2639	0	0	0
T41	203315	0	0	0
T47	65720	0	0	0
T48	0	227	0	0
T54	51609	0	0	0
T62	0	321	0	0
T63	10620	0	0	0
T70	0	186	0	0
T113	0	269	0	0
T114	0	91	0	0
T115	0	110	0	0
T116	0	180	0	0
T117	0	269	0	0
T118	0	305	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316587867	3560	0	0
T6	48714	0	0	0
T7	10873	0	0	0
T11	175738	265	0	0
T24	26113	0	0	0
T25	17964	0	0	0
T28	2639	0	0	0
T41	203315	0	0	0
T47	65720	0	0	0
T48	0	163	0	0
T54	51609	0	0	0
T62	0	236	0	0
T63	10620	0	0	0
T70	0	205	0	0
T113	0	294	0	0
T114	0	87	0	0
T115	0	102	0	0
T116	0	162	0	0
T117	0	281	0	0
T118	0	306	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316587867	4079	0	0
T6	48714	0	0	0
T7	10873	0	0	0
T11	175738	328	0	0
T24	26113	0	0	0
T25	17964	0	0	0
T28	2639	0	0	0
T41	203315	0	0	0
T47	65720	0	0	0
T48	0	263	0	0
T54	51609	0	0	0
T62	0	277	0	0
T63	10620	0	0	0
T70	0	219	0	0
T113	0	236	0	0
T114	0	93	0	0
T115	0	128	0	0
T116	0	118	0	0
T117	0	295	0	0
T118	0	327	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316587867	2615	0	0
T6	48714	0	0	0
T7	10873	0	0	0
T11	175738	216	0	0
T24	26113	0	0	0
T25	17964	0	0	0
T28	2639	0	0	0
T41	203315	0	0	0
T47	65720	0	0	0
T48	0	218	0	0
T54	51609	0	0	0
T62	0	254	0	0
T63	10620	0	0	0
T70	0	216	0	0
T113	0	223	0	0
T114	0	65	0	0
T115	0	82	0	0
T116	0	164	0	0
T117	0	250	0	0
T118	0	311	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316587867	2143	0	0
T6	48714	0	0	0
T7	10873	0	0	0
T11	175738	193	0	0
T24	26113	0	0	0
T25	17964	0	0	0
T28	2639	0	0	0
T41	203315	0	0	0
T47	65720	0	0	0
T48	0	157	0	0
T54	51609	0	0	0
T62	0	232	0	0
T63	10620	0	0	0
T70	0	110	0	0
T113	0	236	0	0
T114	0	97	0	0
T115	0	68	0	0
T116	0	105	0	0
T117	0	191	0	0
T118	0	184	0	0