SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1792 | 1792 | 0 | 0 |
OutputsKnown_A | 630736430 | 630529922 | 0 | 0 |
gen_flops.OutputDelay_A | 315368215 | 315251963 | 0 | 2688 |
gen_no_flops.OutputDelay_A | 315368215 | 315264961 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1792 | 1792 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 630736430 | 630529922 | 0 | 0 |
T1 | 58340 | 58178 | 0 | 0 |
T2 | 153880 | 153714 | 0 | 0 |
T3 | 25316 | 25130 | 0 | 0 |
T4 | 563368 | 563216 | 0 | 0 |
T5 | 31056 | 30868 | 0 | 0 |
T6 | 97428 | 97076 | 0 | 0 |
T8 | 4070 | 3934 | 0 | 0 |
T9 | 8308 | 8166 | 0 | 0 |
T10 | 270140 | 270024 | 0 | 0 |
T11 | 351476 | 351116 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 315368215 | 315251963 | 0 | 2688 |
T1 | 29170 | 29086 | 0 | 3 |
T2 | 76940 | 76854 | 0 | 3 |
T3 | 12658 | 12542 | 0 | 3 |
T4 | 281684 | 281605 | 0 | 3 |
T5 | 15528 | 15431 | 0 | 3 |
T6 | 48714 | 48440 | 0 | 3 |
T8 | 2035 | 1964 | 0 | 3 |
T9 | 4154 | 4080 | 0 | 3 |
T10 | 135070 | 135009 | 0 | 3 |
T11 | 175738 | 175525 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 315368215 | 315264961 | 0 | 0 |
T1 | 29170 | 29089 | 0 | 0 |
T2 | 76940 | 76857 | 0 | 0 |
T3 | 12658 | 12565 | 0 | 0 |
T4 | 281684 | 281608 | 0 | 0 |
T5 | 15528 | 15434 | 0 | 0 |
T6 | 48714 | 48538 | 0 | 0 |
T8 | 2035 | 1967 | 0 | 0 |
T9 | 4154 | 4083 | 0 | 0 |
T10 | 135070 | 135012 | 0 | 0 |
T11 | 175738 | 175558 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 896 | 896 | 0 | 0 |
OutputsKnown_A | 315368215 | 315264961 | 0 | 0 |
gen_flops.OutputDelay_A | 315368215 | 315251963 | 0 | 2688 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 896 | 896 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 315368215 | 315264961 | 0 | 0 |
T1 | 29170 | 29089 | 0 | 0 |
T2 | 76940 | 76857 | 0 | 0 |
T3 | 12658 | 12565 | 0 | 0 |
T4 | 281684 | 281608 | 0 | 0 |
T5 | 15528 | 15434 | 0 | 0 |
T6 | 48714 | 48538 | 0 | 0 |
T8 | 2035 | 1967 | 0 | 0 |
T9 | 4154 | 4083 | 0 | 0 |
T10 | 135070 | 135012 | 0 | 0 |
T11 | 175738 | 175558 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 315368215 | 315251963 | 0 | 2688 |
T1 | 29170 | 29086 | 0 | 3 |
T2 | 76940 | 76854 | 0 | 3 |
T3 | 12658 | 12542 | 0 | 3 |
T4 | 281684 | 281605 | 0 | 3 |
T5 | 15528 | 15431 | 0 | 3 |
T6 | 48714 | 48440 | 0 | 3 |
T8 | 2035 | 1964 | 0 | 3 |
T9 | 4154 | 4080 | 0 | 3 |
T10 | 135070 | 135009 | 0 | 3 |
T11 | 175738 | 175525 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 896 | 896 | 0 | 0 |
OutputsKnown_A | 315368215 | 315264961 | 0 | 0 |
gen_no_flops.OutputDelay_A | 315368215 | 315264961 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 896 | 896 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 315368215 | 315264961 | 0 | 0 |
T1 | 29170 | 29089 | 0 | 0 |
T2 | 76940 | 76857 | 0 | 0 |
T3 | 12658 | 12565 | 0 | 0 |
T4 | 281684 | 281608 | 0 | 0 |
T5 | 15528 | 15434 | 0 | 0 |
T6 | 48714 | 48538 | 0 | 0 |
T8 | 2035 | 1967 | 0 | 0 |
T9 | 4154 | 4083 | 0 | 0 |
T10 | 135070 | 135012 | 0 | 0 |
T11 | 175738 | 175558 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 315368215 | 315264961 | 0 | 0 |
T1 | 29170 | 29089 | 0 | 0 |
T2 | 76940 | 76857 | 0 | 0 |
T3 | 12658 | 12565 | 0 | 0 |
T4 | 281684 | 281608 | 0 | 0 |
T5 | 15528 | 15434 | 0 | 0 |
T6 | 48714 | 48538 | 0 | 0 |
T8 | 2035 | 1967 | 0 | 0 |
T9 | 4154 | 4083 | 0 | 0 |
T10 | 135070 | 135012 | 0 | 0 |
T11 | 175738 | 175558 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |