| T789 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.862271719 |
|
|
Jul 30 07:30:20 PM PDT 24 |
Jul 30 07:51:35 PM PDT 24 |
3058419983 ps |
| T790 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2351754495 |
|
|
Jul 30 07:27:36 PM PDT 24 |
Jul 30 07:27:40 PM PDT 24 |
243636202 ps |
| T791 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.1623918372 |
|
|
Jul 30 07:26:51 PM PDT 24 |
Jul 30 07:26:52 PM PDT 24 |
51771218 ps |
| T792 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.527450376 |
|
|
Jul 30 07:28:02 PM PDT 24 |
Jul 30 07:32:37 PM PDT 24 |
5673686989 ps |
| T793 |
/workspace/coverage/default/10.sram_ctrl_executable.733968094 |
|
|
Jul 30 07:24:45 PM PDT 24 |
Jul 30 07:51:16 PM PDT 24 |
23459253236 ps |
| T794 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3033050577 |
|
|
Jul 30 07:24:06 PM PDT 24 |
Jul 30 07:29:44 PM PDT 24 |
19728643046 ps |
| T795 |
/workspace/coverage/default/37.sram_ctrl_executable.2221096349 |
|
|
Jul 30 07:29:14 PM PDT 24 |
Jul 30 07:31:54 PM PDT 24 |
6187122189 ps |
| T796 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3849542374 |
|
|
Jul 30 07:29:45 PM PDT 24 |
Jul 30 07:29:49 PM PDT 24 |
381674239 ps |
| T797 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1049207671 |
|
|
Jul 30 07:27:44 PM PDT 24 |
Jul 30 08:00:17 PM PDT 24 |
16321017885 ps |
| T798 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3768565463 |
|
|
Jul 30 07:27:52 PM PDT 24 |
Jul 30 07:34:22 PM PDT 24 |
3983053480 ps |
| T799 |
/workspace/coverage/default/22.sram_ctrl_regwen.3239743272 |
|
|
Jul 30 07:26:40 PM PDT 24 |
Jul 30 07:38:48 PM PDT 24 |
7995072898 ps |
| T800 |
/workspace/coverage/default/46.sram_ctrl_bijection.2509816150 |
|
|
Jul 30 07:30:59 PM PDT 24 |
Jul 30 07:31:45 PM PDT 24 |
4846974468 ps |
| T801 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1477953064 |
|
|
Jul 30 07:28:32 PM PDT 24 |
Jul 30 07:29:11 PM PDT 24 |
405270469 ps |
| T802 |
/workspace/coverage/default/45.sram_ctrl_regwen.3022083267 |
|
|
Jul 30 07:30:56 PM PDT 24 |
Jul 30 07:59:24 PM PDT 24 |
41963640992 ps |
| T803 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2066173302 |
|
|
Jul 30 07:31:06 PM PDT 24 |
Jul 30 07:31:23 PM PDT 24 |
1112166818 ps |
| T804 |
/workspace/coverage/default/16.sram_ctrl_executable.3969337818 |
|
|
Jul 30 07:25:40 PM PDT 24 |
Jul 30 07:36:32 PM PDT 24 |
22575070208 ps |
| T805 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1332103893 |
|
|
Jul 30 07:27:25 PM PDT 24 |
Jul 30 07:27:26 PM PDT 24 |
82651128 ps |
| T806 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2455120552 |
|
|
Jul 30 07:24:13 PM PDT 24 |
Jul 30 07:24:18 PM PDT 24 |
183327620 ps |
| T807 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1006976674 |
|
|
Jul 30 07:31:32 PM PDT 24 |
Jul 30 07:31:33 PM PDT 24 |
39329778 ps |
| T808 |
/workspace/coverage/default/37.sram_ctrl_regwen.389163236 |
|
|
Jul 30 07:29:18 PM PDT 24 |
Jul 30 07:38:22 PM PDT 24 |
2720821569 ps |
| T809 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1992876303 |
|
|
Jul 30 07:24:06 PM PDT 24 |
Jul 30 08:45:43 PM PDT 24 |
32973376982 ps |
| T810 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.52195369 |
|
|
Jul 30 07:29:41 PM PDT 24 |
Jul 30 07:29:47 PM PDT 24 |
376866509 ps |
| T811 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2445008283 |
|
|
Jul 30 07:27:16 PM PDT 24 |
Jul 30 07:27:17 PM PDT 24 |
43129460 ps |
| T812 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.3233168939 |
|
|
Jul 30 07:23:56 PM PDT 24 |
Jul 30 07:24:04 PM PDT 24 |
537053304 ps |
| T813 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3441537586 |
|
|
Jul 30 07:31:04 PM PDT 24 |
Jul 30 07:37:13 PM PDT 24 |
62888074321 ps |
| T814 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1509421865 |
|
|
Jul 30 07:25:16 PM PDT 24 |
Jul 30 07:25:17 PM PDT 24 |
23172413 ps |
| T815 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3703014202 |
|
|
Jul 30 07:31:27 PM PDT 24 |
Jul 30 07:41:44 PM PDT 24 |
86551705643 ps |
| T816 |
/workspace/coverage/default/1.sram_ctrl_bijection.541196825 |
|
|
Jul 30 07:23:55 PM PDT 24 |
Jul 30 07:25:01 PM PDT 24 |
1072156912 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4248248323 |
|
|
Jul 30 07:28:41 PM PDT 24 |
Jul 30 07:36:06 PM PDT 24 |
122620397891 ps |
| T818 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2668040759 |
|
|
Jul 30 07:26:50 PM PDT 24 |
Jul 30 07:28:23 PM PDT 24 |
905490353 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3974683136 |
|
|
Jul 30 07:30:56 PM PDT 24 |
Jul 30 07:31:01 PM PDT 24 |
666847168 ps |
| T820 |
/workspace/coverage/default/25.sram_ctrl_regwen.2893574399 |
|
|
Jul 30 07:27:11 PM PDT 24 |
Jul 30 07:48:40 PM PDT 24 |
16487792475 ps |
| T118 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4244100194 |
|
|
Jul 30 07:24:03 PM PDT 24 |
Jul 30 07:27:07 PM PDT 24 |
8874912420 ps |
| T821 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3383820960 |
|
|
Jul 30 07:24:15 PM PDT 24 |
Jul 30 07:25:25 PM PDT 24 |
700156957 ps |
| T822 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1444747342 |
|
|
Jul 30 07:28:27 PM PDT 24 |
Jul 30 08:01:04 PM PDT 24 |
72441615097 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_executable.1674426997 |
|
|
Jul 30 07:30:56 PM PDT 24 |
Jul 30 07:44:45 PM PDT 24 |
4109346359 ps |
| T824 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1168762988 |
|
|
Jul 30 07:27:17 PM PDT 24 |
Jul 30 07:31:40 PM PDT 24 |
6672619457 ps |
| T825 |
/workspace/coverage/default/32.sram_ctrl_bijection.366031753 |
|
|
Jul 30 07:28:16 PM PDT 24 |
Jul 30 07:28:38 PM PDT 24 |
1385854091 ps |
| T826 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1117537016 |
|
|
Jul 30 07:29:53 PM PDT 24 |
Jul 30 07:35:25 PM PDT 24 |
1573649331 ps |
| T827 |
/workspace/coverage/default/48.sram_ctrl_stress_all.803192633 |
|
|
Jul 30 07:31:30 PM PDT 24 |
Jul 30 08:07:39 PM PDT 24 |
16735504524 ps |
| T828 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.396709741 |
|
|
Jul 30 07:27:08 PM PDT 24 |
Jul 30 07:32:16 PM PDT 24 |
3314767356 ps |
| T829 |
/workspace/coverage/default/42.sram_ctrl_smoke.4069224316 |
|
|
Jul 30 07:30:16 PM PDT 24 |
Jul 30 07:32:04 PM PDT 24 |
505275334 ps |
| T830 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3476644567 |
|
|
Jul 30 07:31:14 PM PDT 24 |
Jul 30 07:43:16 PM PDT 24 |
45058888584 ps |
| T831 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3630731508 |
|
|
Jul 30 07:28:25 PM PDT 24 |
Jul 30 07:28:28 PM PDT 24 |
73593398 ps |
| T832 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3509460462 |
|
|
Jul 30 07:29:02 PM PDT 24 |
Jul 30 07:29:08 PM PDT 24 |
2049686979 ps |
| T833 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2889533949 |
|
|
Jul 30 07:25:22 PM PDT 24 |
Jul 30 07:25:25 PM PDT 24 |
56820713 ps |
| T834 |
/workspace/coverage/default/22.sram_ctrl_smoke.3797615607 |
|
|
Jul 30 07:26:35 PM PDT 24 |
Jul 30 07:26:38 PM PDT 24 |
137665860 ps |
| T835 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3780241130 |
|
|
Jul 30 07:26:32 PM PDT 24 |
Jul 30 07:26:40 PM PDT 24 |
892479972 ps |
| T836 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.64258594 |
|
|
Jul 30 07:31:18 PM PDT 24 |
Jul 30 07:31:24 PM PDT 24 |
653656624 ps |
| T837 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1373389106 |
|
|
Jul 30 07:27:55 PM PDT 24 |
Jul 30 07:28:00 PM PDT 24 |
351333520 ps |
| T838 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2264379175 |
|
|
Jul 30 07:30:50 PM PDT 24 |
Jul 30 07:33:59 PM PDT 24 |
4087060879 ps |
| T839 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4185400951 |
|
|
Jul 30 07:31:35 PM PDT 24 |
Jul 30 07:31:36 PM PDT 24 |
213564181 ps |
| T840 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2081585052 |
|
|
Jul 30 07:29:25 PM PDT 24 |
Jul 30 07:30:16 PM PDT 24 |
1464920104 ps |
| T841 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.151163351 |
|
|
Jul 30 07:24:11 PM PDT 24 |
Jul 30 07:28:54 PM PDT 24 |
6254104867 ps |
| T842 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3492104844 |
|
|
Jul 30 07:30:35 PM PDT 24 |
Jul 30 07:30:35 PM PDT 24 |
23893636 ps |
| T843 |
/workspace/coverage/default/40.sram_ctrl_smoke.2734134656 |
|
|
Jul 30 07:29:45 PM PDT 24 |
Jul 30 07:29:48 PM PDT 24 |
388332861 ps |
| T844 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.609254037 |
|
|
Jul 30 07:23:59 PM PDT 24 |
Jul 30 07:24:03 PM PDT 24 |
296531171 ps |
| T845 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1240781194 |
|
|
Jul 30 07:24:19 PM PDT 24 |
Jul 30 07:24:20 PM PDT 24 |
26291320 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.491436478 |
|
|
Jul 30 07:25:48 PM PDT 24 |
Jul 30 07:37:19 PM PDT 24 |
9149118667 ps |
| T847 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3673020905 |
|
|
Jul 30 07:29:51 PM PDT 24 |
Jul 30 07:36:31 PM PDT 24 |
17360626284 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.35586377 |
|
|
Jul 30 07:23:58 PM PDT 24 |
Jul 30 07:24:04 PM PDT 24 |
693985793 ps |
| T849 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.4021978904 |
|
|
Jul 30 07:24:02 PM PDT 24 |
Jul 30 07:24:46 PM PDT 24 |
108167151 ps |
| T850 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1791880485 |
|
|
Jul 30 07:30:10 PM PDT 24 |
Jul 30 07:30:20 PM PDT 24 |
179466454 ps |
| T851 |
/workspace/coverage/default/19.sram_ctrl_smoke.682204079 |
|
|
Jul 30 07:26:07 PM PDT 24 |
Jul 30 07:28:25 PM PDT 24 |
620881322 ps |
| T852 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1676581573 |
|
|
Jul 30 07:26:14 PM PDT 24 |
Jul 30 07:37:56 PM PDT 24 |
10753126925 ps |
| T853 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3629370490 |
|
|
Jul 30 07:23:52 PM PDT 24 |
Jul 30 07:25:54 PM PDT 24 |
1147730820 ps |
| T854 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3439512700 |
|
|
Jul 30 07:28:20 PM PDT 24 |
Jul 30 07:28:24 PM PDT 24 |
920829824 ps |
| T855 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1531989362 |
|
|
Jul 30 07:30:36 PM PDT 24 |
Jul 30 07:30:42 PM PDT 24 |
934099603 ps |
| T856 |
/workspace/coverage/default/32.sram_ctrl_smoke.2993177887 |
|
|
Jul 30 07:28:15 PM PDT 24 |
Jul 30 07:28:22 PM PDT 24 |
1907762207 ps |
| T857 |
/workspace/coverage/default/39.sram_ctrl_executable.4275554244 |
|
|
Jul 30 07:29:40 PM PDT 24 |
Jul 30 07:35:32 PM PDT 24 |
14688067896 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1684088684 |
|
|
Jul 30 07:27:44 PM PDT 24 |
Jul 30 07:27:45 PM PDT 24 |
83736999 ps |
| T859 |
/workspace/coverage/default/26.sram_ctrl_bijection.2422718263 |
|
|
Jul 30 07:27:17 PM PDT 24 |
Jul 30 07:28:08 PM PDT 24 |
8848490983 ps |
| T860 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3033956430 |
|
|
Jul 30 07:25:39 PM PDT 24 |
Jul 30 07:25:40 PM PDT 24 |
75891260 ps |
| T861 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2913582574 |
|
|
Jul 30 07:24:17 PM PDT 24 |
Jul 30 07:24:20 PM PDT 24 |
260196717 ps |
| T862 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3508327854 |
|
|
Jul 30 07:25:33 PM PDT 24 |
Jul 30 08:36:53 PM PDT 24 |
333250461729 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3785297676 |
|
|
Jul 30 07:28:44 PM PDT 24 |
Jul 30 07:34:00 PM PDT 24 |
19033088283 ps |
| T864 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1459421166 |
|
|
Jul 30 07:25:12 PM PDT 24 |
Jul 30 07:27:17 PM PDT 24 |
5855207106 ps |
| T865 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2535587378 |
|
|
Jul 30 07:26:01 PM PDT 24 |
Jul 30 07:26:04 PM PDT 24 |
109883701 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1168252976 |
|
|
Jul 30 07:25:25 PM PDT 24 |
Jul 30 07:27:31 PM PDT 24 |
137336829 ps |
| T867 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.347233839 |
|
|
Jul 30 07:24:09 PM PDT 24 |
Jul 30 07:24:10 PM PDT 24 |
51613751 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_smoke.1390664927 |
|
|
Jul 30 07:31:31 PM PDT 24 |
Jul 30 07:32:36 PM PDT 24 |
472528380 ps |
| T869 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1552534564 |
|
|
Jul 30 07:26:50 PM PDT 24 |
Jul 30 07:26:51 PM PDT 24 |
22272460 ps |
| T870 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2416359574 |
|
|
Jul 30 07:31:34 PM PDT 24 |
Jul 30 07:38:06 PM PDT 24 |
202623339459 ps |
| T871 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2341027084 |
|
|
Jul 30 07:28:37 PM PDT 24 |
Jul 30 08:23:06 PM PDT 24 |
9075466892 ps |
| T872 |
/workspace/coverage/default/2.sram_ctrl_smoke.1718872427 |
|
|
Jul 30 07:23:57 PM PDT 24 |
Jul 30 07:24:32 PM PDT 24 |
401265668 ps |
| T873 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4117035379 |
|
|
Jul 30 07:28:54 PM PDT 24 |
Jul 30 07:30:02 PM PDT 24 |
474766088 ps |
| T874 |
/workspace/coverage/default/23.sram_ctrl_bijection.1647446172 |
|
|
Jul 30 07:26:42 PM PDT 24 |
Jul 30 07:27:34 PM PDT 24 |
842595641 ps |
| T875 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2960969424 |
|
|
Jul 30 07:31:00 PM PDT 24 |
Jul 30 07:31:00 PM PDT 24 |
19018858 ps |
| T876 |
/workspace/coverage/default/30.sram_ctrl_executable.1614133642 |
|
|
Jul 30 07:28:03 PM PDT 24 |
Jul 30 07:31:27 PM PDT 24 |
2155160444 ps |
| T877 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1232826682 |
|
|
Jul 30 07:24:58 PM PDT 24 |
Jul 30 08:18:12 PM PDT 24 |
31504344548 ps |
| T878 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1196705688 |
|
|
Jul 30 07:31:20 PM PDT 24 |
Jul 30 07:31:25 PM PDT 24 |
946536974 ps |
| T879 |
/workspace/coverage/default/27.sram_ctrl_smoke.507863301 |
|
|
Jul 30 07:27:24 PM PDT 24 |
Jul 30 07:27:33 PM PDT 24 |
1909635663 ps |
| T880 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3143148685 |
|
|
Jul 30 07:24:32 PM PDT 24 |
Jul 30 07:24:33 PM PDT 24 |
27567837 ps |
| T881 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3880595950 |
|
|
Jul 30 07:25:21 PM PDT 24 |
Jul 30 07:29:32 PM PDT 24 |
10605615908 ps |
| T882 |
/workspace/coverage/default/34.sram_ctrl_regwen.1724501955 |
|
|
Jul 30 07:28:44 PM PDT 24 |
Jul 30 07:33:51 PM PDT 24 |
6661679186 ps |
| T883 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2142168771 |
|
|
Jul 30 07:26:40 PM PDT 24 |
Jul 30 07:31:41 PM PDT 24 |
12983202868 ps |
| T884 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3701888219 |
|
|
Jul 30 07:24:53 PM PDT 24 |
Jul 30 07:26:14 PM PDT 24 |
2697226774 ps |
| T885 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.780316915 |
|
|
Jul 30 07:31:18 PM PDT 24 |
Jul 30 07:36:42 PM PDT 24 |
6524084585 ps |
| T886 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2971312410 |
|
|
Jul 30 07:29:15 PM PDT 24 |
Jul 30 07:33:01 PM PDT 24 |
2346715619 ps |
| T887 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1652186920 |
|
|
Jul 30 07:30:32 PM PDT 24 |
Jul 30 07:46:03 PM PDT 24 |
4576296058 ps |
| T888 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2254521288 |
|
|
Jul 30 07:28:13 PM PDT 24 |
Jul 30 07:28:18 PM PDT 24 |
207042810 ps |
| T889 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.331859236 |
|
|
Jul 30 07:27:18 PM PDT 24 |
Jul 30 07:36:53 PM PDT 24 |
49623022911 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3173256412 |
|
|
Jul 30 07:30:39 PM PDT 24 |
Jul 30 07:31:27 PM PDT 24 |
138061472 ps |
| T891 |
/workspace/coverage/default/15.sram_ctrl_regwen.799945153 |
|
|
Jul 30 07:25:28 PM PDT 24 |
Jul 30 07:35:09 PM PDT 24 |
16956290303 ps |
| T892 |
/workspace/coverage/default/14.sram_ctrl_executable.2154849051 |
|
|
Jul 30 07:25:16 PM PDT 24 |
Jul 30 07:37:23 PM PDT 24 |
9988947358 ps |
| T893 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2501763765 |
|
|
Jul 30 07:24:14 PM PDT 24 |
Jul 30 07:40:36 PM PDT 24 |
46579940286 ps |
| T894 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2864926714 |
|
|
Jul 30 07:26:39 PM PDT 24 |
Jul 30 07:28:18 PM PDT 24 |
611851800 ps |
| T895 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2038078010 |
|
|
Jul 30 07:30:16 PM PDT 24 |
Jul 30 07:31:54 PM PDT 24 |
601917999 ps |
| T896 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3434034945 |
|
|
Jul 30 07:30:50 PM PDT 24 |
Jul 30 07:34:41 PM PDT 24 |
4837939904 ps |
| T897 |
/workspace/coverage/default/46.sram_ctrl_regwen.96022728 |
|
|
Jul 30 07:31:07 PM PDT 24 |
Jul 30 07:42:53 PM PDT 24 |
11221727968 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3422695908 |
|
|
Jul 30 07:24:55 PM PDT 24 |
Jul 30 07:24:56 PM PDT 24 |
27431060 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1536078161 |
|
|
Jul 30 07:30:55 PM PDT 24 |
Jul 30 07:32:14 PM PDT 24 |
253492333 ps |
| T900 |
/workspace/coverage/default/47.sram_ctrl_smoke.3416206480 |
|
|
Jul 30 07:31:11 PM PDT 24 |
Jul 30 07:31:25 PM PDT 24 |
302942523 ps |
| T901 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1353568820 |
|
|
Jul 30 07:28:05 PM PDT 24 |
Jul 30 07:28:11 PM PDT 24 |
1165549141 ps |
| T902 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2476167651 |
|
|
Jul 30 07:25:21 PM PDT 24 |
Jul 30 07:32:14 PM PDT 24 |
3674853412 ps |
| T903 |
/workspace/coverage/default/34.sram_ctrl_smoke.2073605036 |
|
|
Jul 30 07:28:36 PM PDT 24 |
Jul 30 07:30:58 PM PDT 24 |
143840303 ps |
| T904 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2054051624 |
|
|
Jul 30 07:28:46 PM PDT 24 |
Jul 30 09:03:19 PM PDT 24 |
172144817506 ps |
| T905 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.100634782 |
|
|
Jul 30 07:26:01 PM PDT 24 |
Jul 30 07:32:49 PM PDT 24 |
5041726617 ps |
| T906 |
/workspace/coverage/default/3.sram_ctrl_smoke.1185970092 |
|
|
Jul 30 07:24:04 PM PDT 24 |
Jul 30 07:24:08 PM PDT 24 |
216394719 ps |
| T907 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3907254354 |
|
|
Jul 30 07:25:53 PM PDT 24 |
Jul 30 07:26:49 PM PDT 24 |
2691405270 ps |
| T908 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2934419111 |
|
|
Jul 30 07:30:22 PM PDT 24 |
Jul 30 07:30:28 PM PDT 24 |
569812964 ps |
| T909 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.126635260 |
|
|
Jul 30 07:24:25 PM PDT 24 |
Jul 30 07:26:32 PM PDT 24 |
151589989 ps |
| T910 |
/workspace/coverage/default/27.sram_ctrl_regwen.693695360 |
|
|
Jul 30 07:27:32 PM PDT 24 |
Jul 30 07:38:26 PM PDT 24 |
6634463358 ps |
| T911 |
/workspace/coverage/default/11.sram_ctrl_smoke.3178710414 |
|
|
Jul 30 07:24:49 PM PDT 24 |
Jul 30 07:25:00 PM PDT 24 |
611261859 ps |
| T912 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.320223851 |
|
|
Jul 30 07:23:50 PM PDT 24 |
Jul 30 07:23:51 PM PDT 24 |
31742531 ps |
| T913 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1293377759 |
|
|
Jul 30 07:25:49 PM PDT 24 |
Jul 30 07:25:54 PM PDT 24 |
388656112 ps |
| T914 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1800101643 |
|
|
Jul 30 07:28:11 PM PDT 24 |
Jul 30 07:44:59 PM PDT 24 |
24494618916 ps |
| T915 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.377117596 |
|
|
Jul 30 07:25:18 PM PDT 24 |
Jul 30 07:31:48 PM PDT 24 |
1784636471 ps |
| T916 |
/workspace/coverage/default/1.sram_ctrl_executable.893292216 |
|
|
Jul 30 07:23:52 PM PDT 24 |
Jul 30 07:27:36 PM PDT 24 |
10461402072 ps |
| T917 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2521465325 |
|
|
Jul 30 07:28:20 PM PDT 24 |
Jul 30 07:43:14 PM PDT 24 |
8235161036 ps |
| T918 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2308004979 |
|
|
Jul 30 07:29:53 PM PDT 24 |
Jul 30 07:30:03 PM PDT 24 |
175111840 ps |
| T919 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2283111661 |
|
|
Jul 30 07:30:46 PM PDT 24 |
Jul 30 07:30:47 PM PDT 24 |
18634498 ps |
| T920 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1269511737 |
|
|
Jul 30 07:23:52 PM PDT 24 |
Jul 30 07:23:53 PM PDT 24 |
25371060 ps |
| T921 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.96762448 |
|
|
Jul 30 07:25:49 PM PDT 24 |
Jul 30 07:27:09 PM PDT 24 |
162014407 ps |
| T922 |
/workspace/coverage/default/38.sram_ctrl_smoke.1046302711 |
|
|
Jul 30 07:29:22 PM PDT 24 |
Jul 30 07:30:02 PM PDT 24 |
199457212 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1935434762 |
|
|
Jul 30 07:27:00 PM PDT 24 |
Jul 30 07:27:56 PM PDT 24 |
184818325 ps |
| T924 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2200614146 |
|
|
Jul 30 07:24:19 PM PDT 24 |
Jul 30 08:02:15 PM PDT 24 |
141841484967 ps |
| T925 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.928224787 |
|
|
Jul 30 07:31:21 PM PDT 24 |
Jul 30 07:37:42 PM PDT 24 |
3863231250 ps |
| T926 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3264578778 |
|
|
Jul 30 07:26:10 PM PDT 24 |
Jul 30 07:26:18 PM PDT 24 |
2614596779 ps |
| T927 |
/workspace/coverage/default/4.sram_ctrl_bijection.110389727 |
|
|
Jul 30 07:24:07 PM PDT 24 |
Jul 30 07:25:15 PM PDT 24 |
11532741570 ps |
| T928 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.778147733 |
|
|
Jul 30 07:25:05 PM PDT 24 |
Jul 30 07:29:39 PM PDT 24 |
3353784250 ps |
| T929 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4231344203 |
|
|
Jul 30 07:24:48 PM PDT 24 |
Jul 30 07:26:29 PM PDT 24 |
2164386378 ps |
| T930 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3772177273 |
|
|
Jul 30 07:24:08 PM PDT 24 |
Jul 30 07:24:40 PM PDT 24 |
754931229 ps |
| T931 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2241568882 |
|
|
Jul 30 07:31:35 PM PDT 24 |
Jul 30 07:40:40 PM PDT 24 |
10605895737 ps |
| T932 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1956582704 |
|
|
Jul 30 07:24:00 PM PDT 24 |
Jul 30 07:24:00 PM PDT 24 |
61296365 ps |
| T933 |
/workspace/coverage/default/35.sram_ctrl_executable.1753667821 |
|
|
Jul 30 07:28:53 PM PDT 24 |
Jul 30 07:42:41 PM PDT 24 |
6912333033 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.421119804 |
|
|
Jul 30 07:22:36 PM PDT 24 |
Jul 30 07:22:39 PM PDT 24 |
348609535 ps |
| T934 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.39357650 |
|
|
Jul 30 07:22:55 PM PDT 24 |
Jul 30 07:22:57 PM PDT 24 |
32376240 ps |
| T68 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3965653002 |
|
|
Jul 30 07:23:01 PM PDT 24 |
Jul 30 07:23:02 PM PDT 24 |
13933297 ps |
| T69 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.187192106 |
|
|
Jul 30 07:22:59 PM PDT 24 |
Jul 30 07:23:00 PM PDT 24 |
29012494 ps |
| T73 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1161029550 |
|
|
Jul 30 07:23:07 PM PDT 24 |
Jul 30 07:23:10 PM PDT 24 |
396458719 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3184156833 |
|
|
Jul 30 07:22:46 PM PDT 24 |
Jul 30 07:22:48 PM PDT 24 |
167228729 ps |
| T74 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3993780115 |
|
|
Jul 30 07:23:08 PM PDT 24 |
Jul 30 07:23:10 PM PDT 24 |
1717325987 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2828958198 |
|
|
Jul 30 07:22:43 PM PDT 24 |
Jul 30 07:22:43 PM PDT 24 |
11473004 ps |
| T76 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3149949619 |
|
|
Jul 30 07:22:57 PM PDT 24 |
Jul 30 07:22:57 PM PDT 24 |
11953378 ps |
| T65 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3883199913 |
|
|
Jul 30 07:22:56 PM PDT 24 |
Jul 30 07:22:57 PM PDT 24 |
118459924 ps |
| T111 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1591109843 |
|
|
Jul 30 07:23:01 PM PDT 24 |
Jul 30 07:23:01 PM PDT 24 |
24841309 ps |
| T112 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3747943056 |
|
|
Jul 30 07:22:41 PM PDT 24 |
Jul 30 07:22:43 PM PDT 24 |
456013784 ps |
| T77 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.747308985 |
|
|
Jul 30 07:23:04 PM PDT 24 |
Jul 30 07:23:06 PM PDT 24 |
407262838 ps |
| T935 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1854122711 |
|
|
Jul 30 07:22:35 PM PDT 24 |
Jul 30 07:22:36 PM PDT 24 |
239134062 ps |
| T936 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1198771140 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:09 PM PDT 24 |
86783644 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1318158542 |
|
|
Jul 30 07:22:45 PM PDT 24 |
Jul 30 07:22:47 PM PDT 24 |
722346371 ps |
| T103 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3492892709 |
|
|
Jul 30 07:22:59 PM PDT 24 |
Jul 30 07:23:00 PM PDT 24 |
19513198 ps |
| T66 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.56665386 |
|
|
Jul 30 07:23:00 PM PDT 24 |
Jul 30 07:23:02 PM PDT 24 |
436269081 ps |
| T938 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1665851655 |
|
|
Jul 30 07:22:38 PM PDT 24 |
Jul 30 07:22:40 PM PDT 24 |
238896482 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.683946462 |
|
|
Jul 30 07:22:30 PM PDT 24 |
Jul 30 07:22:31 PM PDT 24 |
18516112 ps |
| T939 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1319261965 |
|
|
Jul 30 07:23:04 PM PDT 24 |
Jul 30 07:23:05 PM PDT 24 |
18027746 ps |
| T940 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.495336199 |
|
|
Jul 30 07:23:04 PM PDT 24 |
Jul 30 07:23:06 PM PDT 24 |
33604933 ps |
| T119 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3177015474 |
|
|
Jul 30 07:23:08 PM PDT 24 |
Jul 30 07:23:10 PM PDT 24 |
304299414 ps |
| T941 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2263407972 |
|
|
Jul 30 07:22:39 PM PDT 24 |
Jul 30 07:22:39 PM PDT 24 |
15134869 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2495278978 |
|
|
Jul 30 07:22:51 PM PDT 24 |
Jul 30 07:22:53 PM PDT 24 |
75176355 ps |
| T120 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1496320906 |
|
|
Jul 30 07:22:57 PM PDT 24 |
Jul 30 07:22:59 PM PDT 24 |
405026494 ps |
| T79 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2468933545 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:08 PM PDT 24 |
293742677 ps |
| T104 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2104630209 |
|
|
Jul 30 07:23:08 PM PDT 24 |
Jul 30 07:23:09 PM PDT 24 |
18397409 ps |
| T80 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2042324626 |
|
|
Jul 30 07:22:51 PM PDT 24 |
Jul 30 07:22:53 PM PDT 24 |
291314626 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4174853567 |
|
|
Jul 30 07:22:36 PM PDT 24 |
Jul 30 07:22:37 PM PDT 24 |
363696729 ps |
| T125 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.808219724 |
|
|
Jul 30 07:23:14 PM PDT 24 |
Jul 30 07:23:16 PM PDT 24 |
284139155 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2787219299 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:08 PM PDT 24 |
466634354 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1735334846 |
|
|
Jul 30 07:22:35 PM PDT 24 |
Jul 30 07:22:37 PM PDT 24 |
94673048 ps |
| T944 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3295195308 |
|
|
Jul 30 07:23:09 PM PDT 24 |
Jul 30 07:23:15 PM PDT 24 |
1051304122 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2326418851 |
|
|
Jul 30 07:22:37 PM PDT 24 |
Jul 30 07:22:37 PM PDT 24 |
17036519 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1376604451 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:06 PM PDT 24 |
38076252 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2007907877 |
|
|
Jul 30 07:22:53 PM PDT 24 |
Jul 30 07:22:54 PM PDT 24 |
11375913 ps |
| T948 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3570395910 |
|
|
Jul 30 07:22:30 PM PDT 24 |
Jul 30 07:22:31 PM PDT 24 |
20975676 ps |
| T949 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3636827508 |
|
|
Jul 30 07:22:49 PM PDT 24 |
Jul 30 07:22:50 PM PDT 24 |
100758653 ps |
| T950 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1878206122 |
|
|
Jul 30 07:23:07 PM PDT 24 |
Jul 30 07:23:09 PM PDT 24 |
293388885 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3005323116 |
|
|
Jul 30 07:22:53 PM PDT 24 |
Jul 30 07:22:54 PM PDT 24 |
23090832 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3252124575 |
|
|
Jul 30 07:22:57 PM PDT 24 |
Jul 30 07:22:58 PM PDT 24 |
93762940 ps |
| T953 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2880137709 |
|
|
Jul 30 07:22:59 PM PDT 24 |
Jul 30 07:23:04 PM PDT 24 |
496256538 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.850508813 |
|
|
Jul 30 07:23:00 PM PDT 24 |
Jul 30 07:23:04 PM PDT 24 |
67605364 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2291888304 |
|
|
Jul 30 07:22:58 PM PDT 24 |
Jul 30 07:22:59 PM PDT 24 |
40625825 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.900260014 |
|
|
Jul 30 07:22:43 PM PDT 24 |
Jul 30 07:22:44 PM PDT 24 |
17226752 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.543523357 |
|
|
Jul 30 07:23:07 PM PDT 24 |
Jul 30 07:23:08 PM PDT 24 |
16348967 ps |
| T85 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1717499045 |
|
|
Jul 30 07:22:51 PM PDT 24 |
Jul 30 07:22:53 PM PDT 24 |
212433535 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.569087161 |
|
|
Jul 30 07:22:53 PM PDT 24 |
Jul 30 07:22:56 PM PDT 24 |
78908359 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2176511819 |
|
|
Jul 30 07:22:56 PM PDT 24 |
Jul 30 07:23:00 PM PDT 24 |
414983048 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3027909824 |
|
|
Jul 30 07:22:38 PM PDT 24 |
Jul 30 07:22:39 PM PDT 24 |
112684588 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.494049153 |
|
|
Jul 30 07:23:03 PM PDT 24 |
Jul 30 07:23:03 PM PDT 24 |
18021986 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2215247293 |
|
|
Jul 30 07:22:53 PM PDT 24 |
Jul 30 07:22:54 PM PDT 24 |
43804266 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4089300865 |
|
|
Jul 30 07:23:01 PM PDT 24 |
Jul 30 07:23:06 PM PDT 24 |
143016492 ps |
| T95 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1387100764 |
|
|
Jul 30 07:22:51 PM PDT 24 |
Jul 30 07:22:54 PM PDT 24 |
501836344 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2445392695 |
|
|
Jul 30 07:23:13 PM PDT 24 |
Jul 30 07:23:15 PM PDT 24 |
512603615 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2106889102 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:08 PM PDT 24 |
278542918 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.701713954 |
|
|
Jul 30 07:22:42 PM PDT 24 |
Jul 30 07:22:44 PM PDT 24 |
355423593 ps |
| T966 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3269929937 |
|
|
Jul 30 07:23:12 PM PDT 24 |
Jul 30 07:23:13 PM PDT 24 |
69924948 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1482941403 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:08 PM PDT 24 |
90655914 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1579949123 |
|
|
Jul 30 07:22:43 PM PDT 24 |
Jul 30 07:22:46 PM PDT 24 |
750011954 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4063874099 |
|
|
Jul 30 07:23:08 PM PDT 24 |
Jul 30 07:23:09 PM PDT 24 |
48042421 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.333676055 |
|
|
Jul 30 07:22:31 PM PDT 24 |
Jul 30 07:22:34 PM PDT 24 |
1822469823 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2556775288 |
|
|
Jul 30 07:23:06 PM PDT 24 |
Jul 30 07:23:07 PM PDT 24 |
277319247 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3093892045 |
|
|
Jul 30 07:22:38 PM PDT 24 |
Jul 30 07:22:39 PM PDT 24 |
56912678 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3977424401 |
|
|
Jul 30 07:23:06 PM PDT 24 |
Jul 30 07:23:07 PM PDT 24 |
250666424 ps |
| T121 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.352238324 |
|
|
Jul 30 07:22:50 PM PDT 24 |
Jul 30 07:22:52 PM PDT 24 |
232319015 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3469474583 |
|
|
Jul 30 07:23:03 PM PDT 24 |
Jul 30 07:23:04 PM PDT 24 |
33749931 ps |
| T973 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3195299798 |
|
|
Jul 30 07:22:42 PM PDT 24 |
Jul 30 07:22:43 PM PDT 24 |
12775778 ps |
| T974 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3225743232 |
|
|
Jul 30 07:23:12 PM PDT 24 |
Jul 30 07:23:14 PM PDT 24 |
620059878 ps |
| T128 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.688286004 |
|
|
Jul 30 07:22:41 PM PDT 24 |
Jul 30 07:22:42 PM PDT 24 |
353386545 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3245634769 |
|
|
Jul 30 07:23:13 PM PDT 24 |
Jul 30 07:23:13 PM PDT 24 |
12101629 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.785941780 |
|
|
Jul 30 07:22:43 PM PDT 24 |
Jul 30 07:22:45 PM PDT 24 |
317176625 ps |
| T976 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1135070580 |
|
|
Jul 30 07:22:50 PM PDT 24 |
Jul 30 07:22:51 PM PDT 24 |
12633487 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3448801249 |
|
|
Jul 30 07:23:09 PM PDT 24 |
Jul 30 07:23:10 PM PDT 24 |
93987074 ps |
| T978 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1774549961 |
|
|
Jul 30 07:23:08 PM PDT 24 |
Jul 30 07:23:10 PM PDT 24 |
159463274 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1853700729 |
|
|
Jul 30 07:22:35 PM PDT 24 |
Jul 30 07:22:39 PM PDT 24 |
121289079 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2549010388 |
|
|
Jul 30 07:22:57 PM PDT 24 |
Jul 30 07:22:59 PM PDT 24 |
70888060 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1336343795 |
|
|
Jul 30 07:22:30 PM PDT 24 |
Jul 30 07:22:33 PM PDT 24 |
211461481 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3196222869 |
|
|
Jul 30 07:23:00 PM PDT 24 |
Jul 30 07:23:03 PM PDT 24 |
44964883 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2271568576 |
|
|
Jul 30 07:22:58 PM PDT 24 |
Jul 30 07:22:59 PM PDT 24 |
29090420 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3027834162 |
|
|
Jul 30 07:23:05 PM PDT 24 |
Jul 30 07:23:06 PM PDT 24 |
25843910 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1943360232 |
|
|
Jul 30 07:22:56 PM PDT 24 |
Jul 30 07:23:00 PM PDT 24 |
99409437 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3030571973 |
|
|
Jul 30 07:22:49 PM PDT 24 |
Jul 30 07:22:51 PM PDT 24 |
72085014 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3654263313 |
|
|
Jul 30 07:22:45 PM PDT 24 |
Jul 30 07:22:45 PM PDT 24 |
14625558 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1945665838 |
|
|
Jul 30 07:22:38 PM PDT 24 |
Jul 30 07:22:39 PM PDT 24 |
33179301 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4157180587 |
|
|
Jul 30 07:23:02 PM PDT 24 |
Jul 30 07:23:03 PM PDT 24 |
27792917 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4122983399 |
|
|
Jul 30 07:22:30 PM PDT 24 |
Jul 30 07:22:33 PM PDT 24 |
117966499 ps |
| T990 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.265261711 |
|
|
Jul 30 07:23:07 PM PDT 24 |
Jul 30 07:23:08 PM PDT 24 |
171818065 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3998753992 |
|
|
Jul 30 07:22:44 PM PDT 24 |
Jul 30 07:22:44 PM PDT 24 |
16497079 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.695909409 |
|
|
Jul 30 07:22:50 PM PDT 24 |
Jul 30 07:22:51 PM PDT 24 |
26822341 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3024338505 |
|
|
Jul 30 07:22:44 PM PDT 24 |
Jul 30 07:22:48 PM PDT 24 |
415461033 ps |
| T993 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1503232762 |
|
|
Jul 30 07:23:13 PM PDT 24 |
Jul 30 07:23:14 PM PDT 24 |
42534189 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2821683348 |
|
|
Jul 30 07:23:11 PM PDT 24 |
Jul 30 07:23:12 PM PDT 24 |
80859997 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1399363818 |
|
|
Jul 30 07:22:39 PM PDT 24 |
Jul 30 07:22:43 PM PDT 24 |
1744636528 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.660461586 |
|
|
Jul 30 07:22:38 PM PDT 24 |
Jul 30 07:22:41 PM PDT 24 |
1597028790 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.246307656 |
|
|
Jul 30 07:22:53 PM PDT 24 |
Jul 30 07:22:55 PM PDT 24 |
875253397 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.550644168 |
|
|
Jul 30 07:22:57 PM PDT 24 |
Jul 30 07:22:59 PM PDT 24 |
862377820 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1666332287 |
|
|
Jul 30 07:22:36 PM PDT 24 |
Jul 30 07:22:37 PM PDT 24 |
172439698 ps |
| T999 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4279559305 |
|
|
Jul 30 07:22:59 PM PDT 24 |
Jul 30 07:23:02 PM PDT 24 |
412563973 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1898196740 |
|
|
Jul 30 07:22:36 PM PDT 24 |
Jul 30 07:22:37 PM PDT 24 |
69487510 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1229308897 |
|
|
Jul 30 07:22:58 PM PDT 24 |
Jul 30 07:22:59 PM PDT 24 |
25676839 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2781354715 |
|
|
Jul 30 07:22:45 PM PDT 24 |
Jul 30 07:22:46 PM PDT 24 |
144381971 ps |
| T1003 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4203499054 |
|
|
Jul 30 07:22:55 PM PDT 24 |
Jul 30 07:22:58 PM PDT 24 |
1409323982 ps |