Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14470187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

63550083

1

T1

3071

T2

9874

T3

6664

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38909805	1			T1	1024		T2	5003		T3	3641
values[0x0]	18108811	1			T1	1064		T2	2408		T3	1789
values[0x1]	21001654	1			T1	983		T2	2463		T3	1886

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7208205	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

70812065

1

T1

3071

T2

9874

T3

6987

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	311048	1			T1	12		T3	22		T5	526
valid_sources[0x01]	296379	1			T1	13		T3	39		T5	543
valid_sources[0x02]	333411	1			T1	11		T3	13		T5	514
valid_sources[0x03]	269708	1			T1	6		T3	36		T5	484
valid_sources[0x04]	264742	1			T1	7		T3	22		T5	563
valid_sources[0x05]	285874	1			T1	12		T3	24		T5	556
valid_sources[0x06]	278425	1			T1	15		T3	41		T5	513
valid_sources[0x07]	277263	1			T1	11		T3	18		T5	579
valid_sources[0x08]	291218	1			T1	9		T3	28		T5	553
valid_sources[0x09]	279779	1			T1	14		T3	24		T5	552
valid_sources[0x0a]	273751	1			T1	10		T3	26		T5	572
valid_sources[0x0b]	265157	1			T1	11		T3	26		T5	566
valid_sources[0x0c]	319500	1			T1	13		T3	20		T5	556
valid_sources[0x0d]	276733	1			T1	11		T3	46		T5	510
valid_sources[0x0e]	332941	1			T1	14		T3	24		T5	549
valid_sources[0x0f]	311800	1			T1	11		T3	27		T5	576
valid_sources[0x10]	383709	1			T1	10		T3	20		T5	477
valid_sources[0x11]	300495	1			T1	10		T3	32		T5	552
valid_sources[0x12]	326756	1			T1	10		T3	44		T5	558
valid_sources[0x13]	407786	1			T1	12		T3	24		T5	542
valid_sources[0x14]	268233	1			T1	10		T3	27		T5	554
valid_sources[0x15]	371113	1			T1	14		T3	39		T5	506
valid_sources[0x16]	275816	1			T1	10		T3	31		T5	535
valid_sources[0x17]	285793	1			T1	19		T3	23		T5	531
valid_sources[0x18]	320778	1			T1	12		T3	23		T5	523
valid_sources[0x19]	349119	1			T1	8		T3	34		T5	524
valid_sources[0x1a]	273892	1			T1	13		T3	40		T5	575
valid_sources[0x1b]	369421	1			T1	13		T3	28		T5	519
valid_sources[0x1c]	277784	1			T1	12		T3	31		T5	525
valid_sources[0x1d]	288684	1			T1	9		T3	41		T5	548
valid_sources[0x1e]	290776	1			T1	22		T3	25		T5	532
valid_sources[0x1f]	269563	1			T1	16		T3	23		T5	515
valid_sources[0x20]	314933	1			T1	14		T3	23		T5	504
valid_sources[0x21]	391904	1			T1	5		T3	28		T5	588
valid_sources[0x22]	297705	1			T1	12		T3	20		T5	493
valid_sources[0x23]	371437	1			T1	11		T3	22		T5	577
valid_sources[0x24]	294150	1			T1	11		T3	37		T5	563
valid_sources[0x25]	298934	1			T1	13		T3	27		T5	572
valid_sources[0x26]	311428	1			T1	13		T2	4937		T3	26
valid_sources[0x27]	274390	1			T1	4		T3	26		T5	493
valid_sources[0x28]	277514	1			T1	9		T3	22		T5	512
valid_sources[0x29]	338622	1			T1	7		T3	12		T5	547
valid_sources[0x2a]	306621	1			T1	10		T3	22		T5	523
valid_sources[0x2b]	300459	1			T1	7		T3	37		T5	505
valid_sources[0x2c]	287983	1			T1	11		T3	23		T5	588
valid_sources[0x2d]	289134	1			T1	7		T3	23		T5	549
valid_sources[0x2e]	264401	1			T1	14		T3	14		T5	508
valid_sources[0x2f]	275213	1			T1	14		T3	31		T5	545
valid_sources[0x30]	328478	1			T1	7		T3	29		T5	524
valid_sources[0x31]	290919	1			T1	13		T3	27		T5	581
valid_sources[0x32]	281230	1			T1	16		T3	43		T5	550
valid_sources[0x33]	321276	1			T1	11		T3	19		T5	558
valid_sources[0x34]	338640	1			T1	14		T3	47		T5	529
valid_sources[0x35]	378475	1			T1	10		T3	15		T5	482
valid_sources[0x36]	268461	1			T1	15		T3	30		T5	573
valid_sources[0x37]	338879	1			T1	17		T3	31		T5	533
valid_sources[0x38]	328418	1			T1	5		T3	30		T5	517
valid_sources[0x39]	343160	1			T1	11		T3	32		T5	498
valid_sources[0x3a]	289113	1			T1	10		T3	31		T5	557
valid_sources[0x3b]	331335	1			T1	12		T3	22		T5	559
valid_sources[0x3c]	344809	1			T1	15		T3	31		T5	516
valid_sources[0x3d]	279348	1			T1	9		T3	36		T5	536
valid_sources[0x3e]	324557	1			T1	8		T3	25		T5	544
valid_sources[0x3f]	302125	1			T1	16		T3	35		T5	591
valid_sources[0x40]	311635	1			T1	23		T3	38		T5	560
valid_sources[0x41]	300380	1			T1	8		T3	44		T5	564
valid_sources[0x42]	331049	1			T1	12		T3	20		T5	526
valid_sources[0x43]	336038	1			T1	13		T3	36		T5	524
valid_sources[0x44]	278208	1			T1	4		T3	30		T5	521
valid_sources[0x45]	288806	1			T1	21		T3	25		T5	513
valid_sources[0x46]	257267	1			T1	16		T3	30		T5	535
valid_sources[0x47]	267220	1			T1	15		T3	24		T5	547
valid_sources[0x48]	281783	1			T1	8		T2	4937		T3	33
valid_sources[0x49]	311443	1			T1	12		T3	39		T5	519
valid_sources[0x4a]	298997	1			T1	14		T3	27		T5	553
valid_sources[0x4b]	314628	1			T1	15		T3	16		T5	563
valid_sources[0x4c]	330891	1			T1	8		T3	29		T5	536
valid_sources[0x4d]	318501	1			T1	13		T3	29		T5	532
valid_sources[0x4e]	310113	1			T1	6		T3	24		T5	527
valid_sources[0x4f]	371615	1			T1	9		T3	21		T5	527
valid_sources[0x50]	253700	1			T1	11		T3	28		T5	525
valid_sources[0x51]	273614	1			T1	5		T3	41		T5	542
valid_sources[0x52]	292052	1			T1	10		T3	27		T5	540
valid_sources[0x53]	270057	1			T1	19		T3	23		T5	550
valid_sources[0x54]	265782	1			T1	19		T3	19		T5	532
valid_sources[0x55]	307301	1			T1	9		T3	25		T5	561
valid_sources[0x56]	337084	1			T1	9		T3	34		T5	565
valid_sources[0x57]	267689	1			T1	13		T3	36		T5	536
valid_sources[0x58]	278860	1			T1	13		T3	27		T5	537
valid_sources[0x59]	263825	1			T1	12		T3	15		T5	552
valid_sources[0x5a]	343635	1			T1	9		T3	42		T5	532
valid_sources[0x5b]	286956	1			T1	12		T3	24		T5	539
valid_sources[0x5c]	326631	1			T1	15		T3	33		T5	525
valid_sources[0x5d]	277579	1			T1	18		T3	26		T5	515
valid_sources[0x5e]	311164	1			T1	13		T3	29		T5	527
valid_sources[0x5f]	358143	1			T1	14		T3	26		T5	568
valid_sources[0x60]	306357	1			T1	11		T3	23		T5	528
valid_sources[0x61]	276986	1			T1	11		T3	32		T5	521
valid_sources[0x62]	256370	1			T1	13		T3	28		T5	553
valid_sources[0x63]	277202	1			T1	12		T3	37		T5	542
valid_sources[0x64]	259880	1			T1	14		T3	20		T5	552
valid_sources[0x65]	355770	1			T1	15		T3	27		T5	537
valid_sources[0x66]	316303	1			T1	19		T3	27		T5	577
valid_sources[0x67]	303774	1			T1	13		T3	34		T5	574
valid_sources[0x68]	271681	1			T1	11		T3	42		T5	538
valid_sources[0x69]	307901	1			T1	17		T3	29		T5	571
valid_sources[0x6a]	316213	1			T1	15		T3	41		T5	529
valid_sources[0x6b]	309007	1			T1	17		T3	53		T5	553
valid_sources[0x6c]	289028	1			T1	20		T3	28		T5	579
valid_sources[0x6d]	271666	1			T1	14		T3	31		T5	523
valid_sources[0x6e]	265781	1			T1	14		T3	27		T5	574
valid_sources[0x6f]	334152	1			T1	10		T3	49		T5	575
valid_sources[0x70]	308242	1			T1	16		T3	26		T5	547
valid_sources[0x71]	324553	1			T1	15		T3	32		T5	528
valid_sources[0x72]	331456	1			T1	11		T3	36		T5	513
valid_sources[0x73]	334823	1			T1	5		T3	32		T5	562
valid_sources[0x74]	298550	1			T1	16		T3	33		T5	558
valid_sources[0x75]	276091	1			T1	10		T3	25		T5	583
valid_sources[0x76]	288221	1			T1	13		T3	32		T5	592
valid_sources[0x77]	328973	1			T1	14		T3	34		T5	511
valid_sources[0x78]	280253	1			T1	7		T3	22		T5	515
valid_sources[0x79]	284194	1			T1	16		T3	48		T5	537
valid_sources[0x7a]	268909	1			T1	11		T3	23		T5	555
valid_sources[0x7b]	343410	1			T1	12		T3	27		T5	568
valid_sources[0x7c]	311145	1			T1	8		T3	25		T5	547
valid_sources[0x7d]	296977	1			T1	8		T3	20		T5	480
valid_sources[0x7e]	281605	1			T1	11		T3	35		T5	508
valid_sources[0x7f]	340322	1			T1	19		T3	25		T5	540
valid_sources[0x80]	262978	1			T1	10		T3	27		T5	529

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31680141

1

T1

1024

T2

5003

T3

3313

values[0x0]

all_enables

biggest_size

15936785

1

T1

1064

T2

2408

T3

1685

values[0x1]

all_enables

biggest_size

15933157

1

T1

983

T2

2463

T3

1666

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

109757

1

T2

1

T3

1

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43479	1			T6	32		T23	513		T18	18
values[0x0]	49466	1			T1	4		T2	1		T4	2
values[0x1]	52822	1			T2	1		T3	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

117976

1

T2

1

T3

1

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	762	1			T23	6		T18	1		T21	5
valid_sources[0x01]	491	1			T23	17		T18	1		T8	2
valid_sources[0x02]	436	1			T23	12		T21	5		T25	15
valid_sources[0x03]	485	1			T24	6		T23	5		T18	1
valid_sources[0x04]	449	1			T10	1		T75	2		T23	2
valid_sources[0x05]	564	1			T23	5		T18	1		T21	5
valid_sources[0x06]	480	1			T24	3		T23	10		T8	1
valid_sources[0x07]	457	1			T1	4		T23	4		T18	1
valid_sources[0x08]	781	1			T45	1		T23	17		T21	4
valid_sources[0x09]	498	1			T47	1		T23	31		T86	1
valid_sources[0x0a]	706	1			T24	8		T23	14		T21	12
valid_sources[0x0b]	569	1			T23	8		T21	4		T25	1
valid_sources[0x0c]	552	1			T23	21		T21	8		T26	1
valid_sources[0x0d]	620	1			T23	11		T21	3		T26	2
valid_sources[0x0e]	548	1			T23	1		T21	6		T25	1
valid_sources[0x0f]	563	1			T23	1		T18	1		T77	1
valid_sources[0x10]	561	1			T53	1		T23	14		T21	11
valid_sources[0x11]	558	1			T23	4		T8	1		T21	13
valid_sources[0x12]	516	1			T47	1		T23	1		T18	1
valid_sources[0x13]	789	1			T10	1		T53	1		T23	3
valid_sources[0x14]	749	1			T45	1		T23	12		T18	1
valid_sources[0x15]	610	1			T23	3		T18	1		T21	14
valid_sources[0x16]	528	1			T21	7		T25	4		T59	7
valid_sources[0x17]	642	1			T23	7		T21	5		T25	5
valid_sources[0x18]	520	1			T23	6		T21	7		T48	1
valid_sources[0x19]	590	1			T23	3		T21	5		T25	4
valid_sources[0x1a]	695	1			T23	2		T18	2		T21	5
valid_sources[0x1b]	401	1			T23	9		T18	2		T21	4
valid_sources[0x1c]	542	1			T6	65		T23	8		T18	1
valid_sources[0x1d]	537	1			T23	14		T21	7		T25	8
valid_sources[0x1e]	453	1			T23	1		T8	1		T21	6
valid_sources[0x1f]	509	1			T23	11		T21	8		T25	7
valid_sources[0x20]	604	1			T2	1		T23	5		T8	1
valid_sources[0x21]	785	1			T47	1		T23	12		T8	1
valid_sources[0x22]	632	1			T23	4		T21	4		T78	5
valid_sources[0x23]	923	1			T23	13		T21	14		T22	61
valid_sources[0x24]	793	1			T23	9		T82	1		T21	13
valid_sources[0x25]	769	1			T23	16		T21	9		T59	56
valid_sources[0x26]	399	1			T23	8		T21	3		T25	12
valid_sources[0x27]	758	1			T23	9		T18	3		T21	7
valid_sources[0x28]	571	1			T23	5		T18	1		T21	5
valid_sources[0x29]	783	1			T23	2		T7	5		T8	1
valid_sources[0x2a]	555	1			T23	5		T21	4		T25	3
valid_sources[0x2b]	686	1			T23	12		T18	1		T8	1
valid_sources[0x2c]	410	1			T23	4		T21	7		T25	12
valid_sources[0x2d]	618	1			T23	15		T21	1		T25	4
valid_sources[0x2e]	666	1			T11	1		T23	8		T21	5
valid_sources[0x2f]	657	1			T11	1		T24	2		T23	4
valid_sources[0x30]	378	1			T53	4		T23	3		T18	1
valid_sources[0x31]	576	1			T65	2		T23	20		T21	7
valid_sources[0x32]	706	1			T23	17		T21	5		T25	4
valid_sources[0x33]	366	1			T23	11		T21	3		T25	3
valid_sources[0x34]	636	1			T23	8		T21	7		T25	6
valid_sources[0x35]	474	1			T23	1		T21	1		T25	8
valid_sources[0x36]	529	1			T23	13		T21	8		T25	9
valid_sources[0x37]	389	1			T23	3		T8	1		T21	3
valid_sources[0x38]	470	1			T9	1		T23	5		T21	6
valid_sources[0x39]	424	1			T23	8		T21	6		T25	12
valid_sources[0x3a]	491	1			T23	18		T18	1		T21	1
valid_sources[0x3b]	859	1			T23	5		T21	11		T87	195
valid_sources[0x3c]	541	1			T23	12		T18	3		T85	1
valid_sources[0x3d]	483	1			T24	7		T23	7		T18	1
valid_sources[0x3e]	556	1			T23	7		T21	7		T48	1
valid_sources[0x3f]	504	1			T23	14		T82	1		T21	2
valid_sources[0x40]	665	1			T23	5		T21	6		T26	3
valid_sources[0x41]	688	1			T23	7		T18	1		T21	11
valid_sources[0x42]	462	1			T11	1		T23	2		T21	8
valid_sources[0x43]	442	1			T11	1		T23	1		T8	2
valid_sources[0x44]	506	1			T23	18		T18	1		T21	7
valid_sources[0x45]	436	1			T9	1		T23	12		T21	7
valid_sources[0x46]	395	1			T23	14		T18	1		T21	9
valid_sources[0x47]	520	1			T27	3		T23	4		T8	1
valid_sources[0x48]	628	1			T45	1		T23	5		T8	1
valid_sources[0x49]	432	1			T23	10		T21	4		T25	4
valid_sources[0x4a]	627	1			T23	2		T18	1		T21	9
valid_sources[0x4b]	649	1			T42	1		T23	2		T21	4
valid_sources[0x4c]	427	1			T23	2		T21	7		T25	3
valid_sources[0x4d]	522	1			T23	9		T21	6		T150	2
valid_sources[0x4e]	749	1			T45	1		T23	7		T21	5
valid_sources[0x4f]	515	1			T24	1		T23	9		T21	5
valid_sources[0x50]	464	1			T23	1		T21	4		T25	8
valid_sources[0x51]	469	1			T45	1		T23	8		T8	1
valid_sources[0x52]	409	1			T23	10		T21	6		T26	1
valid_sources[0x53]	527	1			T23	10		T21	7		T59	3
valid_sources[0x54]	639	1			T23	5		T18	1		T21	4
valid_sources[0x55]	692	1			T23	2		T18	1		T20	110
valid_sources[0x56]	469	1			T23	9		T21	4		T48	1
valid_sources[0x57]	461	1			T23	10		T82	1		T21	10
valid_sources[0x58]	532	1			T23	6		T21	8		T59	7
valid_sources[0x59]	402	1			T23	2		T21	6		T26	4
valid_sources[0x5a]	378	1			T23	10		T18	2		T21	5
valid_sources[0x5b]	777	1			T23	1		T21	7		T151	1
valid_sources[0x5c]	429	1			T23	10		T21	3		T25	7
valid_sources[0x5d]	605	1			T10	1		T23	12		T21	10
valid_sources[0x5e]	872	1			T23	2		T8	2		T21	6
valid_sources[0x5f]	439	1			T23	6		T21	6		T25	8
valid_sources[0x60]	419	1			T14	1		T23	6		T8	1
valid_sources[0x61]	457	1			T4	3		T23	13		T8	2
valid_sources[0x62]	428	1			T23	23		T21	5		T25	1
valid_sources[0x63]	831	1			T11	1		T27	1		T23	7
valid_sources[0x64]	497	1			T23	1		T18	1		T21	6
valid_sources[0x65]	643	1			T10	1		T23	9		T8	2
valid_sources[0x66]	622	1			T27	1		T45	1		T23	4
valid_sources[0x67]	556	1			T57	2		T24	4		T23	6
valid_sources[0x68]	880	1			T23	6		T8	1		T21	5
valid_sources[0x69]	518	1			T23	3		T21	11		T26	1
valid_sources[0x6a]	532	1			T23	3		T21	5		T59	1
valid_sources[0x6b]	413	1			T23	8		T21	7		T25	2
valid_sources[0x6c]	597	1			T10	1		T23	5		T21	7
valid_sources[0x6d]	536	1			T23	7		T18	2		T21	9
valid_sources[0x6e]	478	1			T23	3		T18	1		T21	7
valid_sources[0x6f]	458	1			T23	25		T21	3		T25	16
valid_sources[0x70]	513	1			T23	6		T21	6		T25	3
valid_sources[0x71]	496	1			T12	1		T23	5		T21	12
valid_sources[0x72]	831	1			T23	7		T21	7		T71	393
valid_sources[0x73]	596	1			T23	1		T21	10		T25	16
valid_sources[0x74]	501	1			T23	2		T21	9		T25	6
valid_sources[0x75]	447	1			T23	18		T21	4		T25	6
valid_sources[0x76]	597	1			T14	1		T23	3		T21	4
valid_sources[0x77]	641	1			T23	8		T82	2		T21	8
valid_sources[0x78]	749	1			T23	6		T21	6		T25	9
valid_sources[0x79]	548	1			T23	4		T18	1		T21	6
valid_sources[0x7a]	433	1			T23	2		T21	6		T25	7
valid_sources[0x7b]	462	1			T23	16		T18	1		T21	5
valid_sources[0x7c]	621	1			T23	16		T18	1		T8	2
valid_sources[0x7d]	621	1			T23	11		T21	8		T151	1
valid_sources[0x7e]	454	1			T23	2		T21	2		T26	1
valid_sources[0x7f]	506	1			T2	1		T67	1		T23	10
valid_sources[0x80]	1102	1			T23	2		T18	2		T86	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31036

1

T6

20

T23

463

T18

11

values[0x0]

all_enables

biggest_size

40600

1

T2

1

T4

2

T5

5

values[0x1]

all_enables

biggest_size

38121

1

T3

1

T10

2

T14

1