Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14024832

1

T3

652

T5

12588

T9

18105

full_word

57554872

1

T1

3071

T2

9874

T3

6664

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	71579404	1			T1	3071		T2	9874		T3	7316
auto[TlIntgErrCmd]	96	1			T68	4		T69	9		T70	7
auto[TlIntgErrData]	106	1			T68	8		T69	6		T70	7
auto[TlIntgErrBoth]	98	1			T68	8		T69	5		T70	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32440895

1

T1

1024

T2

5003

T3

3641

auto[1]

39138809

1

T1

2047

T2

4871

T3

3675

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6669343	1			T3	328		T5	6281		T9	9027
auto[TlIntgErrNone]	partial	auto[1]	7355222	1			T3	324		T5	6307		T9	9078
auto[TlIntgErrNone]	full_word	auto[0]	25771419	1			T1	1024		T2	5003		T3	3313
auto[TlIntgErrNone]	full_word	auto[1]	31783420	1			T1	2047		T2	4871		T3	3351
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T68	2		T69	3		T70	4
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T68	2		T69	6		T70	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T142	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T70	1		T135	2		T138	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T69	5		T70	3		T135	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T68	6		T69	1		T70	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T68	1		T70	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T68	1		T70	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T68	3		T69	1		T70	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T68	5		T69	4		T70	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T135	1		T134	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T135	1		T138	1		T142	1