Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	655286	1			T11	4017		T24	19		T6	25
auto[1]	10238735	1			T2	4999		T3	3628		T5	25994
auto[2]	530694	1			T11	3010		T24	39		T6	20
auto[3]	10119204	1			T2	4870		T3	3664		T5	26079

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13530793	1			T2	9869		T3	6063		T5	43515
auto[1]	2103283	1			T3	580		T5	4092		T9	13761
auto[2]	2110654	1			T3	597		T5	4093		T9	13807
auto[3]	3799189	1			T3	52		T5	373		T9	1391

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8369990

1

T2

9859

T3

7285

T5

52025

auto[1]

13173929

1

T2

10

T3

7

T5

48

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	272551	1			T24	17		T6	21		T67	6
auto[0]	auto[0]	auto[1]	29020	1			T6	2		T67	1		T23	2
auto[0]	auto[0]	auto[2]	29067	1			T24	2		T6	2		T67	1
auto[0]	auto[0]	auto[3]	11831	1			T82	42		T20	8		T26	66
auto[0]	auto[1]	auto[0]	3152687	1			T2	4993		T3	3017		T5	21708
auto[0]	auto[1]	auto[1]	334581	1			T3	284		T5	1922		T42	543
auto[0]	auto[1]	auto[2]	321259	1			T3	301		T5	2149		T9	3
auto[0]	auto[1]	auto[3]	79277	1			T3	25		T5	191		T42	121
auto[0]	auto[2]	auto[0]	232758	1			T6	18		T77	2		T82	2358
auto[0]	auto[2]	auto[1]	24688	1			T82	276		T7	1		T8	2
auto[0]	auto[2]	auto[2]	27195	1			T24	38		T6	1		T67	4
auto[0]	auto[2]	auto[3]	9647	1			T24	1		T6	1		T67	1
auto[0]	auto[3]	auto[0]	3115484	1			T2	4866		T3	3041		T5	21765
auto[0]	auto[3]	auto[1]	317567	1			T3	295		T5	2165		T42	532
auto[0]	auto[3]	auto[2]	332493	1			T3	295		T5	1944		T42	533
auto[0]	auto[3]	auto[3]	79885	1			T3	27		T5	181		T42	134
auto[1]	auto[0]	auto[0]	10598	1			T11	143		T45	963		T82	2
auto[1]	auto[0]	auto[1]	46584	1			T11	585		T45	4284		T26	2
auto[1]	auto[0]	auto[2]	46839	1			T11	601		T45	4292		T26	3
auto[1]	auto[0]	auto[3]	208796	1			T11	2688		T45	19134		T20	1
auto[1]	auto[1]	auto[0]	3373131	1			T2	6		T3	1		T5	22
auto[1]	auto[1]	auto[1]	668448	1			T5	1		T9	6869		T11	1819
auto[1]	auto[1]	auto[2]	660952	1			T9	6928		T11	1124		T13	5201
auto[1]	auto[1]	auto[3]	1648400	1			T5	1		T9	685		T11	8252
auto[1]	auto[2]	auto[0]	7639	1			T45	866		T82	4		T26	7
auto[1]	auto[2]	auto[1]	33642	1			T45	3910		T26	1		T121	4400
auto[1]	auto[2]	auto[2]	35080	1			T11	551		T45	2939		T82	1
auto[1]	auto[2]	auto[3]	160045	1			T11	2459		T45	13078		T121	14694
auto[1]	auto[3]	auto[0]	3365945	1			T2	4		T3	4		T5	20
auto[1]	auto[3]	auto[1]	648753	1			T3	1		T5	4		T9	6892
auto[1]	auto[3]	auto[2]	657769	1			T3	1		T9	6876		T11	1799
auto[1]	auto[3]	auto[3]	1601308	1			T9	706		T11	7845		T13	21292