Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	331221569	163287	0	0
ctrl_regwen_rd_A	331221569	2506	0	0
exec_rd_A	331221569	2033	0	0
exec_regwen_rd_A	331221569	2322	0	0
readback_rd_A	331221569	1188	0	0
readback_regwen_rd_A	331221569	1070	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331221569	163287	0	0
T18	107668	0	0	0
T21	0	3678	0	0
T23	64774	2440	0	0
T25	0	2121	0	0
T29	2639	0	0	0
T59	0	3247	0	0
T60	0	1921	0	0
T64	0	8855	0	0
T76	11847	0	0	0
T77	4836	0	0	0
T78	0	2260	0	0
T79	0	2072	0	0
T80	0	1160	0	0
T81	0	7460	0	0
T82	134943	0	0	0
T83	12710	0	0	0
T84	8485	0	0	0
T85	61199	0	0	0
T86	1465	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331221569	2506	0	0
T18	107668	0	0	0
T23	64774	199	0	0
T29	2639	0	0	0
T49	0	239	0	0
T50	0	290	0	0
T72	0	65	0	0
T74	0	12	0	0
T76	11847	0	0	0
T77	4836	0	0	0
T82	134943	0	0	0
T83	12710	0	0	0
T84	8485	0	0	0
T85	61199	0	0	0
T86	1465	0	0	0
T125	0	54	0	0
T126	0	202	0	0
T127	0	298	0	0
T128	0	3	0	0
T129	0	9	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331221569	2033	0	0
T18	107668	0	0	0
T23	64774	172	0	0
T29	2639	0	0	0
T49	0	140	0	0
T50	0	230	0	0
T72	0	53	0	0
T74	0	15	0	0
T76	11847	0	0	0
T77	4836	0	0	0
T82	134943	0	0	0
T83	12710	0	0	0
T84	8485	0	0	0
T85	61199	0	0	0
T86	1465	0	0	0
T125	0	60	0	0
T126	0	176	0	0
T127	0	239	0	0
T128	0	3	0	0
T129	0	10	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331221569	2322	0	0
T18	107668	0	0	0
T23	64774	140	0	0
T29	2639	0	0	0
T49	0	212	0	0
T50	0	298	0	0
T72	0	67	0	0
T74	0	5	0	0
T76	11847	0	0	0
T77	4836	0	0	0
T82	134943	0	0	0
T83	12710	0	0	0
T84	8485	0	0	0
T85	61199	0	0	0
T86	1465	0	0	0
T89	0	2	0	0
T125	0	94	0	0
T126	0	170	0	0
T127	0	236	0	0
T128	0	16	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331221569	1188	0	0
T18	107668	0	0	0
T23	64774	166	0	0
T29	2639	0	0	0
T49	0	192	0	0
T50	0	309	0	0
T76	11847	0	0	0
T77	4836	0	0	0
T82	134943	0	0	0
T83	12710	0	0	0
T84	8485	0	0	0
T85	61199	0	0	0
T86	1465	0	0	0
T125	0	72	0	0
T126	0	160	0	0
T127	0	246	0	0
T129	0	8	0	0
T130	0	6	0	0
T131	0	4	0	0
T132	0	5	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331221569	1070	0	0
T18	107668	0	0	0
T23	64774	128	0	0
T29	2639	0	0	0
T49	0	174	0	0
T50	0	264	0	0
T76	11847	0	0	0
T77	4836	0	0	0
T82	134943	0	0	0
T83	12710	0	0	0
T84	8485	0	0	0
T85	61199	0	0	0
T86	1465	0	0	0
T125	0	84	0	0
T126	0	166	0	0
T127	0	219	0	0
T129	0	7	0	0
T132	0	2	0	0
T133	0	3	0	0
T134	0	2	0	0