| T804 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1557277318 |
|
|
Jul 31 07:39:14 PM PDT 24 |
Jul 31 07:42:44 PM PDT 24 |
2268316292 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1898865053 |
|
|
Jul 31 07:39:50 PM PDT 24 |
Jul 31 07:39:57 PM PDT 24 |
1336806803 ps |
| T806 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4027233844 |
|
|
Jul 31 07:39:00 PM PDT 24 |
Jul 31 07:58:04 PM PDT 24 |
122759496073 ps |
| T807 |
/workspace/coverage/default/31.sram_ctrl_stress_all.4033908758 |
|
|
Jul 31 07:41:34 PM PDT 24 |
Jul 31 09:06:18 PM PDT 24 |
34455809254 ps |
| T808 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.577305917 |
|
|
Jul 31 07:41:42 PM PDT 24 |
Jul 31 07:44:27 PM PDT 24 |
1775368769 ps |
| T809 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2777002592 |
|
|
Jul 31 07:40:34 PM PDT 24 |
Jul 31 07:56:58 PM PDT 24 |
36907241274 ps |
| T810 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2481430886 |
|
|
Jul 31 07:42:22 PM PDT 24 |
Jul 31 07:43:55 PM PDT 24 |
534865864 ps |
| T811 |
/workspace/coverage/default/37.sram_ctrl_executable.4069980001 |
|
|
Jul 31 07:42:29 PM PDT 24 |
Jul 31 07:49:06 PM PDT 24 |
46570948731 ps |
| T812 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.309123983 |
|
|
Jul 31 07:40:02 PM PDT 24 |
Jul 31 07:47:02 PM PDT 24 |
1700688447 ps |
| T813 |
/workspace/coverage/default/41.sram_ctrl_regwen.3672260537 |
|
|
Jul 31 07:43:04 PM PDT 24 |
Jul 31 07:53:46 PM PDT 24 |
12744302065 ps |
| T31 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.406372670 |
|
|
Jul 31 07:39:02 PM PDT 24 |
Jul 31 07:39:05 PM PDT 24 |
417979376 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3550462665 |
|
|
Jul 31 07:38:50 PM PDT 24 |
Jul 31 07:41:12 PM PDT 24 |
309977124 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3160485866 |
|
|
Jul 31 07:40:29 PM PDT 24 |
Jul 31 07:45:52 PM PDT 24 |
6569623906 ps |
| T816 |
/workspace/coverage/default/46.sram_ctrl_executable.3086709584 |
|
|
Jul 31 07:43:55 PM PDT 24 |
Jul 31 08:03:52 PM PDT 24 |
56997167654 ps |
| T817 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2891807287 |
|
|
Jul 31 07:39:55 PM PDT 24 |
Jul 31 07:39:56 PM PDT 24 |
11853478 ps |
| T818 |
/workspace/coverage/default/7.sram_ctrl_bijection.164326129 |
|
|
Jul 31 07:39:16 PM PDT 24 |
Jul 31 07:40:07 PM PDT 24 |
12152133660 ps |
| T819 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1493554604 |
|
|
Jul 31 07:39:00 PM PDT 24 |
Jul 31 07:41:01 PM PDT 24 |
204461097 ps |
| T820 |
/workspace/coverage/default/46.sram_ctrl_bijection.251899371 |
|
|
Jul 31 07:43:55 PM PDT 24 |
Jul 31 07:44:19 PM PDT 24 |
540276595 ps |
| T821 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2842341256 |
|
|
Jul 31 07:43:01 PM PDT 24 |
Jul 31 07:43:07 PM PDT 24 |
704689997 ps |
| T822 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2745392570 |
|
|
Jul 31 07:43:27 PM PDT 24 |
Jul 31 07:43:28 PM PDT 24 |
93907796 ps |
| T823 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2183050719 |
|
|
Jul 31 07:43:32 PM PDT 24 |
Jul 31 07:47:21 PM PDT 24 |
9255981722 ps |
| T824 |
/workspace/coverage/default/24.sram_ctrl_bijection.2419461335 |
|
|
Jul 31 07:40:39 PM PDT 24 |
Jul 31 07:40:57 PM PDT 24 |
3191471994 ps |
| T825 |
/workspace/coverage/default/38.sram_ctrl_bijection.67474310 |
|
|
Jul 31 07:42:22 PM PDT 24 |
Jul 31 07:43:10 PM PDT 24 |
4786689452 ps |
| T826 |
/workspace/coverage/default/13.sram_ctrl_bijection.799348985 |
|
|
Jul 31 07:39:32 PM PDT 24 |
Jul 31 07:40:08 PM PDT 24 |
1657519765 ps |
| T827 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3196982285 |
|
|
Jul 31 07:39:13 PM PDT 24 |
Jul 31 07:43:28 PM PDT 24 |
10139731305 ps |
| T828 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3595645402 |
|
|
Jul 31 07:40:33 PM PDT 24 |
Jul 31 07:41:23 PM PDT 24 |
645481289 ps |
| T829 |
/workspace/coverage/default/3.sram_ctrl_executable.3083378461 |
|
|
Jul 31 07:38:57 PM PDT 24 |
Jul 31 07:46:03 PM PDT 24 |
13302576948 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_executable.1970685046 |
|
|
Jul 31 07:39:14 PM PDT 24 |
Jul 31 07:54:22 PM PDT 24 |
58110051537 ps |
| T831 |
/workspace/coverage/default/13.sram_ctrl_executable.2606890439 |
|
|
Jul 31 07:39:34 PM PDT 24 |
Jul 31 07:52:19 PM PDT 24 |
3508130843 ps |
| T832 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3512407635 |
|
|
Jul 31 07:40:52 PM PDT 24 |
Jul 31 07:45:32 PM PDT 24 |
2974910861 ps |
| T833 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.221181058 |
|
|
Jul 31 07:39:47 PM PDT 24 |
Jul 31 07:40:39 PM PDT 24 |
417021587 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2045595929 |
|
|
Jul 31 07:40:09 PM PDT 24 |
Jul 31 07:40:10 PM PDT 24 |
23513517 ps |
| T835 |
/workspace/coverage/default/4.sram_ctrl_stress_all.998981512 |
|
|
Jul 31 07:39:00 PM PDT 24 |
Jul 31 08:30:37 PM PDT 24 |
100063691759 ps |
| T836 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3956744354 |
|
|
Jul 31 07:44:07 PM PDT 24 |
Jul 31 07:44:10 PM PDT 24 |
137780971 ps |
| T837 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.668384278 |
|
|
Jul 31 07:43:21 PM PDT 24 |
Jul 31 07:50:01 PM PDT 24 |
5669156012 ps |
| T838 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.921353266 |
|
|
Jul 31 07:42:01 PM PDT 24 |
Jul 31 07:42:34 PM PDT 24 |
735632598 ps |
| T839 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2071786337 |
|
|
Jul 31 07:39:08 PM PDT 24 |
Jul 31 07:39:18 PM PDT 24 |
186521384 ps |
| T840 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3352269211 |
|
|
Jul 31 07:40:31 PM PDT 24 |
Jul 31 07:40:34 PM PDT 24 |
191718067 ps |
| T841 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.731167896 |
|
|
Jul 31 07:41:13 PM PDT 24 |
Jul 31 07:41:26 PM PDT 24 |
544400941 ps |
| T842 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2806990618 |
|
|
Jul 31 07:41:26 PM PDT 24 |
Jul 31 07:57:13 PM PDT 24 |
16136134991 ps |
| T843 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2939200912 |
|
|
Jul 31 07:38:49 PM PDT 24 |
Jul 31 07:53:50 PM PDT 24 |
10614963384 ps |
| T844 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3324657215 |
|
|
Jul 31 07:40:37 PM PDT 24 |
Jul 31 07:44:27 PM PDT 24 |
13391982953 ps |
| T845 |
/workspace/coverage/default/32.sram_ctrl_regwen.2810035771 |
|
|
Jul 31 07:41:41 PM PDT 24 |
Jul 31 07:54:13 PM PDT 24 |
10449792229 ps |
| T846 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1345708710 |
|
|
Jul 31 07:44:22 PM PDT 24 |
Jul 31 08:07:18 PM PDT 24 |
10019061449 ps |
| T847 |
/workspace/coverage/default/11.sram_ctrl_bijection.2862302768 |
|
|
Jul 31 07:39:20 PM PDT 24 |
Jul 31 07:40:26 PM PDT 24 |
4197286795 ps |
| T848 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1839990929 |
|
|
Jul 31 07:40:51 PM PDT 24 |
Jul 31 08:45:47 PM PDT 24 |
11009504943 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1545347287 |
|
|
Jul 31 07:43:44 PM PDT 24 |
Jul 31 07:43:46 PM PDT 24 |
149044349 ps |
| T850 |
/workspace/coverage/default/27.sram_ctrl_smoke.3735483974 |
|
|
Jul 31 07:41:00 PM PDT 24 |
Jul 31 07:43:31 PM PDT 24 |
537995539 ps |
| T851 |
/workspace/coverage/default/16.sram_ctrl_regwen.681082521 |
|
|
Jul 31 07:39:51 PM PDT 24 |
Jul 31 07:54:37 PM PDT 24 |
10278036417 ps |
| T852 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1646213280 |
|
|
Jul 31 07:43:37 PM PDT 24 |
Jul 31 07:43:41 PM PDT 24 |
94150550 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_alert_test.935506961 |
|
|
Jul 31 07:39:27 PM PDT 24 |
Jul 31 07:39:28 PM PDT 24 |
42100693 ps |
| T854 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.689632587 |
|
|
Jul 31 07:38:57 PM PDT 24 |
Jul 31 07:38:58 PM PDT 24 |
28955386 ps |
| T855 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2505660208 |
|
|
Jul 31 07:40:26 PM PDT 24 |
Jul 31 07:40:31 PM PDT 24 |
70565443 ps |
| T856 |
/workspace/coverage/default/46.sram_ctrl_partial_access.445011695 |
|
|
Jul 31 07:43:58 PM PDT 24 |
Jul 31 07:44:27 PM PDT 24 |
548368942 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.924296854 |
|
|
Jul 31 07:43:38 PM PDT 24 |
Jul 31 07:46:16 PM PDT 24 |
3345140650 ps |
| T858 |
/workspace/coverage/default/37.sram_ctrl_bijection.2899210394 |
|
|
Jul 31 07:42:15 PM PDT 24 |
Jul 31 07:43:16 PM PDT 24 |
5637013053 ps |
| T859 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.657460648 |
|
|
Jul 31 07:40:38 PM PDT 24 |
Jul 31 07:40:46 PM PDT 24 |
2767426523 ps |
| T860 |
/workspace/coverage/default/20.sram_ctrl_regwen.2579202592 |
|
|
Jul 31 07:40:17 PM PDT 24 |
Jul 31 07:56:29 PM PDT 24 |
44261391041 ps |
| T861 |
/workspace/coverage/default/24.sram_ctrl_regwen.599966352 |
|
|
Jul 31 07:40:38 PM PDT 24 |
Jul 31 07:54:14 PM PDT 24 |
22415541800 ps |
| T862 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3624648720 |
|
|
Jul 31 07:39:56 PM PDT 24 |
Jul 31 07:40:07 PM PDT 24 |
214975745 ps |
| T863 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.834019753 |
|
|
Jul 31 07:42:34 PM PDT 24 |
Jul 31 07:51:52 PM PDT 24 |
1491674846 ps |
| T864 |
/workspace/coverage/default/1.sram_ctrl_executable.565308361 |
|
|
Jul 31 07:38:49 PM PDT 24 |
Jul 31 07:56:57 PM PDT 24 |
7310546299 ps |
| T865 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2995853992 |
|
|
Jul 31 07:40:11 PM PDT 24 |
Jul 31 07:40:12 PM PDT 24 |
64710722 ps |
| T866 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1559845970 |
|
|
Jul 31 07:39:53 PM PDT 24 |
Jul 31 07:41:45 PM PDT 24 |
618890305 ps |
| T867 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2778222958 |
|
|
Jul 31 07:39:07 PM PDT 24 |
Jul 31 07:39:10 PM PDT 24 |
58830668 ps |
| T868 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3668223754 |
|
|
Jul 31 07:40:36 PM PDT 24 |
Jul 31 07:42:08 PM PDT 24 |
455950492 ps |
| T869 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2436296455 |
|
|
Jul 31 07:43:14 PM PDT 24 |
Jul 31 07:43:32 PM PDT 24 |
79778201 ps |
| T870 |
/workspace/coverage/default/42.sram_ctrl_smoke.52909172 |
|
|
Jul 31 07:43:08 PM PDT 24 |
Jul 31 07:43:16 PM PDT 24 |
148732830 ps |
| T871 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2181224270 |
|
|
Jul 31 07:39:50 PM PDT 24 |
Jul 31 07:42:24 PM PDT 24 |
1422197690 ps |
| T872 |
/workspace/coverage/default/1.sram_ctrl_smoke.464020590 |
|
|
Jul 31 07:38:39 PM PDT 24 |
Jul 31 07:38:42 PM PDT 24 |
429677395 ps |
| T873 |
/workspace/coverage/default/6.sram_ctrl_bijection.217275979 |
|
|
Jul 31 07:39:06 PM PDT 24 |
Jul 31 07:40:01 PM PDT 24 |
2579377117 ps |
| T874 |
/workspace/coverage/default/29.sram_ctrl_regwen.3537359537 |
|
|
Jul 31 07:41:20 PM PDT 24 |
Jul 31 07:54:34 PM PDT 24 |
55606206295 ps |
| T875 |
/workspace/coverage/default/6.sram_ctrl_regwen.2711373622 |
|
|
Jul 31 07:39:07 PM PDT 24 |
Jul 31 08:03:36 PM PDT 24 |
6973963426 ps |
| T32 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.867484555 |
|
|
Jul 31 07:38:52 PM PDT 24 |
Jul 31 07:38:56 PM PDT 24 |
261779503 ps |
| T876 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3298532123 |
|
|
Jul 31 07:40:46 PM PDT 24 |
Jul 31 07:40:56 PM PDT 24 |
74563285 ps |
| T877 |
/workspace/coverage/default/48.sram_ctrl_executable.348352396 |
|
|
Jul 31 07:44:10 PM PDT 24 |
Jul 31 08:07:44 PM PDT 24 |
92057915782 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.237153395 |
|
|
Jul 31 07:43:13 PM PDT 24 |
Jul 31 07:46:23 PM PDT 24 |
2056013285 ps |
| T879 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2772345474 |
|
|
Jul 31 07:38:49 PM PDT 24 |
Jul 31 07:40:19 PM PDT 24 |
1042310304 ps |
| T880 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3777536647 |
|
|
Jul 31 07:44:11 PM PDT 24 |
Jul 31 07:45:43 PM PDT 24 |
265732166 ps |
| T881 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2770368686 |
|
|
Jul 31 07:41:42 PM PDT 24 |
Jul 31 09:22:20 PM PDT 24 |
60250380998 ps |
| T882 |
/workspace/coverage/default/24.sram_ctrl_smoke.1947613177 |
|
|
Jul 31 07:40:37 PM PDT 24 |
Jul 31 07:42:32 PM PDT 24 |
623150240 ps |
| T883 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.201818047 |
|
|
Jul 31 07:40:34 PM PDT 24 |
Jul 31 07:40:40 PM PDT 24 |
514925355 ps |
| T884 |
/workspace/coverage/default/49.sram_ctrl_bijection.2517554171 |
|
|
Jul 31 07:44:24 PM PDT 24 |
Jul 31 07:45:36 PM PDT 24 |
1284902636 ps |
| T885 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3227899459 |
|
|
Jul 31 07:41:31 PM PDT 24 |
Jul 31 07:41:41 PM PDT 24 |
887755740 ps |
| T886 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.907942700 |
|
|
Jul 31 07:39:27 PM PDT 24 |
Jul 31 07:39:40 PM PDT 24 |
11240651984 ps |
| T887 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1072116175 |
|
|
Jul 31 07:38:49 PM PDT 24 |
Jul 31 07:39:10 PM PDT 24 |
3783589579 ps |
| T888 |
/workspace/coverage/default/26.sram_ctrl_regwen.3033827169 |
|
|
Jul 31 07:40:53 PM PDT 24 |
Jul 31 07:46:14 PM PDT 24 |
6483326499 ps |
| T889 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1844882294 |
|
|
Jul 31 07:41:32 PM PDT 24 |
Jul 31 07:45:03 PM PDT 24 |
8733541812 ps |
| T890 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4294328072 |
|
|
Jul 31 07:39:17 PM PDT 24 |
Jul 31 07:46:26 PM PDT 24 |
62076602935 ps |
| T891 |
/workspace/coverage/default/32.sram_ctrl_executable.3266629089 |
|
|
Jul 31 07:41:42 PM PDT 24 |
Jul 31 07:48:23 PM PDT 24 |
1688290228 ps |
| T892 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2341409041 |
|
|
Jul 31 07:39:34 PM PDT 24 |
Jul 31 07:52:36 PM PDT 24 |
70606514934 ps |
| T893 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.114430049 |
|
|
Jul 31 07:41:12 PM PDT 24 |
Jul 31 07:41:20 PM PDT 24 |
226049374 ps |
| T894 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.384716820 |
|
|
Jul 31 07:40:51 PM PDT 24 |
Jul 31 08:05:24 PM PDT 24 |
22249407907 ps |
| T895 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2585073621 |
|
|
Jul 31 07:39:44 PM PDT 24 |
Jul 31 07:40:55 PM PDT 24 |
645131254 ps |
| T896 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1730297850 |
|
|
Jul 31 07:39:22 PM PDT 24 |
Jul 31 07:39:27 PM PDT 24 |
194486472 ps |
| T897 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1011130948 |
|
|
Jul 31 07:39:28 PM PDT 24 |
Jul 31 09:07:53 PM PDT 24 |
128899950092 ps |
| T898 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1936587959 |
|
|
Jul 31 07:40:10 PM PDT 24 |
Jul 31 07:42:42 PM PDT 24 |
1628944606 ps |
| T899 |
/workspace/coverage/default/36.sram_ctrl_smoke.188019198 |
|
|
Jul 31 07:42:06 PM PDT 24 |
Jul 31 07:42:20 PM PDT 24 |
637000775 ps |
| T900 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.836698424 |
|
|
Jul 31 07:40:38 PM PDT 24 |
Jul 31 07:40:39 PM PDT 24 |
107253345 ps |
| T901 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.122485622 |
|
|
Jul 31 07:38:43 PM PDT 24 |
Jul 31 07:40:38 PM PDT 24 |
476148462 ps |
| T902 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1827720160 |
|
|
Jul 31 07:39:01 PM PDT 24 |
Jul 31 07:39:04 PM PDT 24 |
390329990 ps |
| T903 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1435617104 |
|
|
Jul 31 07:42:35 PM PDT 24 |
Jul 31 07:42:45 PM PDT 24 |
611859403 ps |
| T904 |
/workspace/coverage/default/5.sram_ctrl_smoke.2545204111 |
|
|
Jul 31 07:38:59 PM PDT 24 |
Jul 31 07:39:13 PM PDT 24 |
920437392 ps |
| T905 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2223875714 |
|
|
Jul 31 07:41:01 PM PDT 24 |
Jul 31 07:41:06 PM PDT 24 |
95241968 ps |
| T906 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4073464326 |
|
|
Jul 31 07:39:35 PM PDT 24 |
Jul 31 07:58:42 PM PDT 24 |
57428768102 ps |
| T907 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.255350262 |
|
|
Jul 31 07:40:54 PM PDT 24 |
Jul 31 07:41:37 PM PDT 24 |
109546986 ps |
| T908 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2485099255 |
|
|
Jul 31 07:39:49 PM PDT 24 |
Jul 31 07:43:16 PM PDT 24 |
2154055767 ps |
| T909 |
/workspace/coverage/default/3.sram_ctrl_regwen.8241925 |
|
|
Jul 31 07:39:00 PM PDT 24 |
Jul 31 08:06:30 PM PDT 24 |
9592722558 ps |
| T104 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3010188045 |
|
|
Jul 31 07:41:49 PM PDT 24 |
Jul 31 07:41:54 PM PDT 24 |
94079516 ps |
| T910 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3382750688 |
|
|
Jul 31 07:39:34 PM PDT 24 |
Jul 31 07:39:58 PM PDT 24 |
200092574 ps |
| T911 |
/workspace/coverage/default/38.sram_ctrl_alert_test.3189926922 |
|
|
Jul 31 07:42:29 PM PDT 24 |
Jul 31 07:42:30 PM PDT 24 |
41024246 ps |
| T912 |
/workspace/coverage/default/12.sram_ctrl_smoke.2286182767 |
|
|
Jul 31 07:39:28 PM PDT 24 |
Jul 31 07:39:41 PM PDT 24 |
3690679550 ps |
| T913 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1580332508 |
|
|
Jul 31 07:43:14 PM PDT 24 |
Jul 31 07:43:15 PM PDT 24 |
17068590 ps |
| T914 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2960679222 |
|
|
Jul 31 07:39:06 PM PDT 24 |
Jul 31 07:41:45 PM PDT 24 |
284484671 ps |
| T915 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3967258074 |
|
|
Jul 31 07:40:08 PM PDT 24 |
Jul 31 08:22:25 PM PDT 24 |
153879457782 ps |
| T916 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1913264718 |
|
|
Jul 31 07:39:27 PM PDT 24 |
Jul 31 07:48:09 PM PDT 24 |
164108779225 ps |
| T917 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2348663915 |
|
|
Jul 31 07:39:29 PM PDT 24 |
Jul 31 07:39:55 PM PDT 24 |
100724420 ps |
| T918 |
/workspace/coverage/default/19.sram_ctrl_bijection.1258159175 |
|
|
Jul 31 07:40:11 PM PDT 24 |
Jul 31 07:40:31 PM PDT 24 |
884930524 ps |
| T919 |
/workspace/coverage/default/9.sram_ctrl_bijection.1585583159 |
|
|
Jul 31 07:39:19 PM PDT 24 |
Jul 31 07:40:18 PM PDT 24 |
3341287247 ps |
| T920 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3691269643 |
|
|
Jul 31 07:40:31 PM PDT 24 |
Jul 31 07:40:32 PM PDT 24 |
75646100 ps |
| T921 |
/workspace/coverage/default/10.sram_ctrl_alert_test.433431322 |
|
|
Jul 31 07:39:28 PM PDT 24 |
Jul 31 07:39:29 PM PDT 24 |
19939628 ps |
| T922 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1666576457 |
|
|
Jul 31 07:39:10 PM PDT 24 |
Jul 31 07:40:28 PM PDT 24 |
2730000031 ps |
| T923 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3102665238 |
|
|
Jul 31 07:38:58 PM PDT 24 |
Jul 31 07:46:03 PM PDT 24 |
6550936122 ps |
| T924 |
/workspace/coverage/default/48.sram_ctrl_smoke.279691846 |
|
|
Jul 31 07:44:09 PM PDT 24 |
Jul 31 07:46:26 PM PDT 24 |
591751064 ps |
| T925 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.987235444 |
|
|
Jul 31 07:38:49 PM PDT 24 |
Jul 31 07:38:54 PM PDT 24 |
98225920 ps |
| T926 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1184728775 |
|
|
Jul 31 07:41:00 PM PDT 24 |
Jul 31 08:10:13 PM PDT 24 |
181505534333 ps |
| T927 |
/workspace/coverage/default/34.sram_ctrl_bijection.3710307993 |
|
|
Jul 31 07:41:49 PM PDT 24 |
Jul 31 07:42:50 PM PDT 24 |
5114001213 ps |
| T928 |
/workspace/coverage/default/42.sram_ctrl_executable.1338719310 |
|
|
Jul 31 07:43:07 PM PDT 24 |
Jul 31 07:58:34 PM PDT 24 |
46679635512 ps |
| T929 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.100237560 |
|
|
Jul 31 07:43:24 PM PDT 24 |
Jul 31 07:43:32 PM PDT 24 |
704104411 ps |
| T930 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2884198417 |
|
|
Jul 31 07:44:09 PM PDT 24 |
Jul 31 07:46:31 PM PDT 24 |
2999042796 ps |
| T931 |
/workspace/coverage/default/0.sram_ctrl_partial_access.805806393 |
|
|
Jul 31 07:38:50 PM PDT 24 |
Jul 31 07:40:39 PM PDT 24 |
345670485 ps |
| T932 |
/workspace/coverage/default/49.sram_ctrl_executable.3504273455 |
|
|
Jul 31 07:44:23 PM PDT 24 |
Jul 31 07:50:11 PM PDT 24 |
6879955980 ps |
| T933 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1012421075 |
|
|
Jul 31 07:41:24 PM PDT 24 |
Jul 31 07:41:24 PM PDT 24 |
50281148 ps |
| T934 |
/workspace/coverage/default/34.sram_ctrl_smoke.3414272058 |
|
|
Jul 31 07:41:51 PM PDT 24 |
Jul 31 07:43:01 PM PDT 24 |
894673166 ps |
| T935 |
/workspace/coverage/default/33.sram_ctrl_smoke.2687646946 |
|
|
Jul 31 07:41:40 PM PDT 24 |
Jul 31 07:41:41 PM PDT 24 |
179852750 ps |
| T936 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.675861800 |
|
|
Jul 31 07:40:16 PM PDT 24 |
Jul 31 07:44:09 PM PDT 24 |
4528777085 ps |
| T937 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3289148178 |
|
|
Jul 31 07:40:45 PM PDT 24 |
Jul 31 07:42:08 PM PDT 24 |
1003358998 ps |
| T938 |
/workspace/coverage/default/23.sram_ctrl_partial_access.3946249234 |
|
|
Jul 31 07:40:37 PM PDT 24 |
Jul 31 07:40:48 PM PDT 24 |
159576541 ps |
| T939 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1377535951 |
|
|
Jul 31 07:38:49 PM PDT 24 |
Jul 31 07:39:47 PM PDT 24 |
342276403 ps |
| T940 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.291286574 |
|
|
Jul 31 07:41:50 PM PDT 24 |
Jul 31 07:46:09 PM PDT 24 |
10782502895 ps |
| T941 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3658546344 |
|
|
Jul 31 07:43:56 PM PDT 24 |
Jul 31 08:00:31 PM PDT 24 |
5468647079 ps |
| T942 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1539386044 |
|
|
Jul 31 07:39:06 PM PDT 24 |
Jul 31 07:39:31 PM PDT 24 |
228353981 ps |
| T72 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.944583527 |
|
|
Jul 31 05:52:00 PM PDT 24 |
Jul 31 05:52:01 PM PDT 24 |
25982586 ps |
| T73 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2027214606 |
|
|
Jul 31 05:51:43 PM PDT 24 |
Jul 31 05:51:43 PM PDT 24 |
11678039 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2228200459 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
16374380 ps |
| T128 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3155132573 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
35004542 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.724336860 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
25051547 ps |
| T129 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.115699771 |
|
|
Jul 31 05:51:47 PM PDT 24 |
Jul 31 05:51:48 PM PDT 24 |
246279017 ps |
| T943 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2729698515 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:52:01 PM PDT 24 |
639727577 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2635885390 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
69843269 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1778156357 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:52:00 PM PDT 24 |
25839623 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1895210518 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:50 PM PDT 24 |
206200793 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1643799360 |
|
|
Jul 31 05:51:59 PM PDT 24 |
Jul 31 05:52:00 PM PDT 24 |
75171101 ps |
| T946 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3413105685 |
|
|
Jul 31 05:51:59 PM PDT 24 |
Jul 31 05:52:02 PM PDT 24 |
935751819 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1079536792 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:52:00 PM PDT 24 |
29104644 ps |
| T114 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1342506949 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
41882797 ps |
| T115 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1939856961 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
79323800 ps |
| T133 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2920431782 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:50 PM PDT 24 |
37622662 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2743027751 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:50 PM PDT 24 |
17698423 ps |
| T117 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2764884010 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:46 PM PDT 24 |
16430609 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1225976717 |
|
|
Jul 31 05:51:59 PM PDT 24 |
Jul 31 05:52:00 PM PDT 24 |
68418713 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3307516912 |
|
|
Jul 31 05:51:53 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
43545735 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2680376822 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
254368509 ps |
| T92 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4028582788 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:52 PM PDT 24 |
1573626001 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1519140201 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:48 PM PDT 24 |
82429194 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4278291215 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:58 PM PDT 24 |
813795753 ps |
| T119 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1773350220 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
15031921 ps |
| T93 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.972131474 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
216343912 ps |
| T951 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1041052395 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
69882413 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.204114234 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:52:02 PM PDT 24 |
459146220 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2325600895 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:51:57 PM PDT 24 |
41475618 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2011499410 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
55830030 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4220767521 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
84599545 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1843530443 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
470344069 ps |
| T95 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1850770835 |
|
|
Jul 31 05:51:46 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
1578436065 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3121134043 |
|
|
Jul 31 05:51:46 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
22721637 ps |
| T956 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1337661847 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:50 PM PDT 24 |
31321985 ps |
| T69 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.867820583 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:52:01 PM PDT 24 |
686471402 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.48172124 |
|
|
Jul 31 05:51:47 PM PDT 24 |
Jul 31 05:51:48 PM PDT 24 |
23641991 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3829529900 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
21620599 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2842090922 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:51:58 PM PDT 24 |
31871016 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1934473448 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
137098980 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1127572032 |
|
|
Jul 31 05:52:03 PM PDT 24 |
Jul 31 05:52:04 PM PDT 24 |
46662518 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3632009514 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
98599460 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2073244502 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:46 PM PDT 24 |
128617887 ps |
| T97 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2254237109 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:52:01 PM PDT 24 |
1592582717 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4198663178 |
|
|
Jul 31 05:51:39 PM PDT 24 |
Jul 31 05:51:40 PM PDT 24 |
256933212 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.201572583 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
27292190 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3914843179 |
|
|
Jul 31 05:51:47 PM PDT 24 |
Jul 31 05:51:50 PM PDT 24 |
568292188 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2619884500 |
|
|
Jul 31 05:51:51 PM PDT 24 |
Jul 31 05:51:53 PM PDT 24 |
155537826 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3390026533 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:51:57 PM PDT 24 |
40352126 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.384728721 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
14558383 ps |
| T967 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3757617662 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:53 PM PDT 24 |
362445163 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1116965128 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
15088379 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.215729749 |
|
|
Jul 31 05:51:53 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
339319640 ps |
| T970 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2262798690 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:58 PM PDT 24 |
165862524 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1163367090 |
|
|
Jul 31 05:51:52 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
446159987 ps |
| T135 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3483358961 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
333513735 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3212948477 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
126268782 ps |
| T139 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1606174947 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
310599817 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4190034126 |
|
|
Jul 31 05:51:46 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
19726542 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.955069523 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
34343762 ps |
| T134 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1131323783 |
|
|
Jul 31 05:52:02 PM PDT 24 |
Jul 31 05:52:09 PM PDT 24 |
260164052 ps |
| T973 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.773742629 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
117724259 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2730158687 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:54 PM PDT 24 |
67869508 ps |
| T975 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1829210824 |
|
|
Jul 31 05:51:53 PM PDT 24 |
Jul 31 05:51:53 PM PDT 24 |
55604563 ps |
| T976 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2140199140 |
|
|
Jul 31 05:51:47 PM PDT 24 |
Jul 31 05:51:48 PM PDT 24 |
110265568 ps |
| T137 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3231096370 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:52:02 PM PDT 24 |
219372865 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2598647241 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
101590025 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4125332657 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:52:02 PM PDT 24 |
463072441 ps |
| T130 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3643276064 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
353502979 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3190444792 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
413803310 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3306312413 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
267389624 ps |
| T981 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.633378441 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
58433031 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2544694512 |
|
|
Jul 31 05:51:48 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
122432555 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3118731382 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
258164900 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3187751258 |
|
|
Jul 31 05:52:05 PM PDT 24 |
Jul 31 05:52:09 PM PDT 24 |
234732123 ps |
| T131 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3005877367 |
|
|
Jul 31 05:52:09 PM PDT 24 |
Jul 31 05:52:11 PM PDT 24 |
834609326 ps |
| T99 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2257737925 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:54 PM PDT 24 |
651843260 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1814517947 |
|
|
Jul 31 05:51:47 PM PDT 24 |
Jul 31 05:51:48 PM PDT 24 |
51210200 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.214658945 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:54 PM PDT 24 |
465959667 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1948378063 |
|
|
Jul 31 05:51:45 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
1514023799 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3370403082 |
|
|
Jul 31 05:51:46 PM PDT 24 |
Jul 31 05:51:47 PM PDT 24 |
14847150 ps |
| T101 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2296271907 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:52 PM PDT 24 |
425672444 ps |
| T988 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.344067835 |
|
|
Jul 31 05:51:42 PM PDT 24 |
Jul 31 05:51:44 PM PDT 24 |
30271775 ps |
| T132 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2040521698 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
803528131 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3972302601 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:53 PM PDT 24 |
89847390 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2255104723 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:50 PM PDT 24 |
14609754 ps |
| T136 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1913757258 |
|
|
Jul 31 05:51:52 PM PDT 24 |
Jul 31 05:51:54 PM PDT 24 |
325287843 ps |
| T991 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.435887030 |
|
|
Jul 31 05:52:08 PM PDT 24 |
Jul 31 05:52:08 PM PDT 24 |
132922102 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3751673769 |
|
|
Jul 31 05:51:43 PM PDT 24 |
Jul 31 05:51:44 PM PDT 24 |
80244287 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4058262306 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:51:58 PM PDT 24 |
35462573 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.15738586 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
24895955 ps |
| T111 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1648472774 |
|
|
Jul 31 05:51:49 PM PDT 24 |
Jul 31 05:51:49 PM PDT 24 |
12271913 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.738732253 |
|
|
Jul 31 05:51:50 PM PDT 24 |
Jul 31 05:51:51 PM PDT 24 |
22020324 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3158510840 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:51:57 PM PDT 24 |
12174122 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4172131300 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:52:01 PM PDT 24 |
16123105 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2585353894 |
|
|
Jul 31 05:51:58 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
41401716 ps |
| T107 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3766470200 |
|
|
Jul 31 05:51:52 PM PDT 24 |
Jul 31 05:51:55 PM PDT 24 |
1385227668 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1553085130 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:51:59 PM PDT 24 |
181808765 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.689589192 |
|
|
Jul 31 05:51:57 PM PDT 24 |
Jul 31 05:51:58 PM PDT 24 |
16032818 ps |
| T1000 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3956777632 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:51:56 PM PDT 24 |
38926904 ps |
| T109 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2198831861 |
|
|
Jul 31 05:51:59 PM PDT 24 |
Jul 31 05:52:03 PM PDT 24 |
1451644609 ps |
| T1001 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2568369571 |
|
|
Jul 31 05:51:59 PM PDT 24 |
Jul 31 05:52:00 PM PDT 24 |
21989422 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1159105684 |
|
|
Jul 31 05:51:46 PM PDT 24 |
Jul 31 05:51:48 PM PDT 24 |
907348506 ps |
| T1003 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.41757184 |
|
|
Jul 31 05:52:01 PM PDT 24 |
Jul 31 05:52:05 PM PDT 24 |
529382872 ps |
| T1004 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2346415831 |
|
|
Jul 31 05:51:56 PM PDT 24 |
Jul 31 05:52:00 PM PDT 24 |
79990194 ps |
| T1005 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3533690847 |
|
|
Jul 31 05:51:55 PM PDT 24 |
Jul 31 05:51:57 PM PDT 24 |
382250060 ps |
| T1006 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1343724461 |
|
|
Jul 31 05:51:54 PM PDT 24 |
Jul 31 05:51:57 PM PDT 24 |
117597201 ps |
| T138 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3840981621 |
|
|
Jul 31 05:51:52 PM PDT 24 |
Jul 31 05:51:54 PM PDT 24 |
1060018811 ps |