Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14444268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59089392

1

T1

18432

T2

10000

T3

162917

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36663405	1			T1	9216		T2	4980		T3	89419
values[0x0]	16990612	1			T1	4591		T2	2496		T3	43539
values[0x1]	19879643	1			T1	4625		T2	2524		T3	46230

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7198562	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66335098

1

T1

18432

T2

10000

T3

171151

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	251297	1			T2	34		T3	692		T4	1102
valid_sources[0x01]	282815	1			T2	36		T3	715		T4	1036
valid_sources[0x02]	255397	1			T2	52		T3	851		T4	927
valid_sources[0x03]	298123	1			T2	26		T3	819		T4	1008
valid_sources[0x04]	252325	1			T2	18		T3	752		T4	987
valid_sources[0x05]	328252	1			T2	25		T3	790		T4	855
valid_sources[0x06]	281439	1			T2	26		T3	610		T4	1036
valid_sources[0x07]	301020	1			T2	10		T3	661		T4	1128
valid_sources[0x08]	293080	1			T2	44		T3	524		T4	983
valid_sources[0x09]	276646	1			T2	33		T3	655		T4	1115
valid_sources[0x0a]	298895	1			T2	32		T3	634		T4	972
valid_sources[0x0b]	310390	1			T2	61		T3	617		T4	949
valid_sources[0x0c]	327544	1			T2	60		T3	826		T4	909
valid_sources[0x0d]	274401	1			T2	42		T3	779		T4	1082
valid_sources[0x0e]	297919	1			T2	44		T3	597		T4	930
valid_sources[0x0f]	260969	1			T2	39		T3	739		T4	1167
valid_sources[0x10]	270976	1			T2	47		T3	740		T4	936
valid_sources[0x11]	292766	1			T2	31		T3	687		T4	1008
valid_sources[0x12]	270528	1			T2	35		T3	662		T4	1037
valid_sources[0x13]	297675	1			T2	29		T3	613		T4	946
valid_sources[0x14]	372888	1			T2	49		T3	671		T4	898
valid_sources[0x15]	264685	1			T2	48		T3	675		T4	1134
valid_sources[0x16]	315247	1			T2	33		T3	781		T4	1013
valid_sources[0x17]	276241	1			T2	30		T3	578		T4	1065
valid_sources[0x18]	284645	1			T2	20		T3	804		T4	1115
valid_sources[0x19]	246081	1			T2	22		T3	689		T4	1092
valid_sources[0x1a]	252463	1			T2	39		T3	652		T4	1244
valid_sources[0x1b]	254474	1			T2	48		T3	850		T4	1116
valid_sources[0x1c]	269017	1			T2	48		T3	923		T4	1102
valid_sources[0x1d]	286878	1			T2	27		T3	622		T4	1133
valid_sources[0x1e]	288875	1			T2	26		T3	593		T4	1129
valid_sources[0x1f]	271214	1			T2	33		T3	708		T4	902
valid_sources[0x20]	343056	1			T2	50		T3	500		T4	1299
valid_sources[0x21]	344446	1			T2	57		T3	778		T4	1255
valid_sources[0x22]	261455	1			T2	43		T3	660		T4	948
valid_sources[0x23]	265125	1			T2	28		T3	595		T4	1065
valid_sources[0x24]	286754	1			T2	44		T3	715		T4	1027
valid_sources[0x25]	292735	1			T2	49		T3	684		T4	907
valid_sources[0x26]	254739	1			T2	45		T3	508		T4	1071
valid_sources[0x27]	274030	1			T2	65		T3	635		T4	1141
valid_sources[0x28]	264211	1			T2	63		T3	756		T4	915
valid_sources[0x29]	292113	1			T2	51		T3	768		T4	965
valid_sources[0x2a]	338669	1			T2	48		T3	738		T4	1052
valid_sources[0x2b]	245756	1			T2	40		T3	848		T4	1266
valid_sources[0x2c]	253920	1			T2	34		T3	684		T4	826
valid_sources[0x2d]	347155	1			T2	53		T3	558		T4	1117
valid_sources[0x2e]	247120	1			T2	32		T3	683		T4	986
valid_sources[0x2f]	292220	1			T2	40		T3	671		T4	1079
valid_sources[0x30]	251209	1			T2	32		T3	667		T4	1133
valid_sources[0x31]	255637	1			T2	29		T3	886		T4	994
valid_sources[0x32]	282593	1			T2	38		T3	581		T4	1108
valid_sources[0x33]	267345	1			T2	26		T3	579		T4	1176
valid_sources[0x34]	262827	1			T2	61		T3	549		T4	962
valid_sources[0x35]	259338	1			T2	48		T3	694		T4	1066
valid_sources[0x36]	275677	1			T2	54		T3	825		T4	1121
valid_sources[0x37]	359599	1			T2	35		T3	869		T4	954
valid_sources[0x38]	282078	1			T2	33		T3	646		T4	1126
valid_sources[0x39]	272916	1			T2	36		T3	572		T4	1193
valid_sources[0x3a]	303037	1			T2	50		T3	730		T4	1135
valid_sources[0x3b]	288008	1			T2	42		T3	542		T4	877
valid_sources[0x3c]	300521	1			T2	50		T3	660		T4	1123
valid_sources[0x3d]	328274	1			T2	58		T3	595		T4	1048
valid_sources[0x3e]	259193	1			T2	25		T3	691		T4	1055
valid_sources[0x3f]	293271	1			T2	47		T3	733		T4	1110
valid_sources[0x40]	270165	1			T2	47		T3	852		T4	1107
valid_sources[0x41]	296864	1			T2	42		T3	738		T4	1323
valid_sources[0x42]	290195	1			T2	28		T3	671		T4	1231
valid_sources[0x43]	284420	1			T2	23		T3	633		T4	915
valid_sources[0x44]	273422	1			T2	43		T3	571		T4	1143
valid_sources[0x45]	266712	1			T2	22		T3	582		T4	1111
valid_sources[0x46]	257241	1			T2	38		T3	796		T4	919
valid_sources[0x47]	276637	1			T2	23		T3	732		T4	988
valid_sources[0x48]	258595	1			T2	52		T3	795		T4	1126
valid_sources[0x49]	261140	1			T2	60		T3	685		T4	993
valid_sources[0x4a]	263186	1			T2	32		T3	850		T4	1066
valid_sources[0x4b]	254998	1			T2	37		T3	654		T4	1123
valid_sources[0x4c]	253577	1			T2	30		T3	756		T4	1076
valid_sources[0x4d]	256700	1			T2	63		T3	683		T4	1043
valid_sources[0x4e]	284144	1			T2	36		T3	604		T4	1243
valid_sources[0x4f]	321690	1			T2	48		T3	641		T4	842
valid_sources[0x50]	332094	1			T2	38		T3	665		T4	1205
valid_sources[0x51]	242598	1			T2	54		T3	766		T4	1028
valid_sources[0x52]	289491	1			T2	26		T3	620		T4	791
valid_sources[0x53]	295866	1			T2	38		T3	717		T4	1251
valid_sources[0x54]	254062	1			T2	67		T3	691		T4	1031
valid_sources[0x55]	308442	1			T2	35		T3	595		T4	1013
valid_sources[0x56]	299072	1			T2	34		T3	650		T4	1015
valid_sources[0x57]	333181	1			T2	39		T3	693		T4	1090
valid_sources[0x58]	298407	1			T2	61		T3	586		T4	1118
valid_sources[0x59]	279266	1			T2	33		T3	716		T4	1063
valid_sources[0x5a]	256114	1			T2	39		T3	690		T4	1164
valid_sources[0x5b]	277881	1			T2	36		T3	806		T4	1123
valid_sources[0x5c]	267717	1			T2	34		T3	707		T4	953
valid_sources[0x5d]	271087	1			T2	55		T3	591		T4	1030
valid_sources[0x5e]	299578	1			T2	32		T3	657		T4	1343
valid_sources[0x5f]	401710	1			T2	58		T3	739		T4	1279
valid_sources[0x60]	314374	1			T2	28		T3	593		T4	1213
valid_sources[0x61]	255900	1			T2	34		T3	782		T4	1163
valid_sources[0x62]	285969	1			T2	38		T3	853		T4	1178
valid_sources[0x63]	269615	1			T2	39		T3	843		T4	924
valid_sources[0x64]	278212	1			T2	46		T3	823		T4	1081
valid_sources[0x65]	359227	1			T2	53		T3	646		T4	1159
valid_sources[0x66]	250661	1			T2	31		T3	644		T4	1152
valid_sources[0x67]	252378	1			T2	48		T3	785		T4	779
valid_sources[0x68]	290997	1			T2	51		T3	554		T4	961
valid_sources[0x69]	290886	1			T2	42		T3	826		T4	1139
valid_sources[0x6a]	290266	1			T2	20		T3	615		T4	940
valid_sources[0x6b]	314466	1			T2	42		T3	759		T4	982
valid_sources[0x6c]	263591	1			T2	30		T3	604		T4	1191
valid_sources[0x6d]	259784	1			T2	28		T3	651		T4	783
valid_sources[0x6e]	300038	1			T2	35		T3	799		T4	1225
valid_sources[0x6f]	318837	1			T2	42		T3	698		T4	1020
valid_sources[0x70]	290644	1			T2	35		T3	708		T4	1043
valid_sources[0x71]	307462	1			T2	46		T3	753		T4	1241
valid_sources[0x72]	261986	1			T2	18		T3	864		T4	959
valid_sources[0x73]	292229	1			T2	38		T3	607		T4	1036
valid_sources[0x74]	251127	1			T2	27		T3	491		T4	989
valid_sources[0x75]	258409	1			T2	41		T3	693		T4	1096
valid_sources[0x76]	285005	1			T2	46		T3	670		T4	909
valid_sources[0x77]	298344	1			T2	31		T3	719		T4	1006
valid_sources[0x78]	270937	1			T2	36		T3	755		T4	1081
valid_sources[0x79]	247674	1			T2	27		T3	700		T4	1105
valid_sources[0x7a]	264214	1			T2	60		T3	583		T4	988
valid_sources[0x7b]	258607	1			T2	44		T3	731		T4	1077
valid_sources[0x7c]	269103	1			T2	47		T3	893		T4	1162
valid_sources[0x7d]	313084	1			T2	27		T3	956		T4	1025
valid_sources[0x7e]	296247	1			T2	20		T3	676		T4	1173
valid_sources[0x7f]	337972	1			T2	28		T3	718		T4	1050
valid_sources[0x80]	292238	1			T2	17		T3	763		T4	943

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29448803

1

T1

9216

T2

4980

T3

81265

values[0x0]

all_enables

biggest_size

14818634

1

T1

4591

T2

2496

T3

41144

values[0x1]

all_enables

biggest_size

14821955

1

T1

4625

T2

2524

T3

40508

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35256	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132411

1

T1

2

T3

5

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48851	1			T5	720		T22	8		T20	19
values[0x0]	57521	1			T1	6		T3	10		T4	2
values[0x1]	61295	1			T1	3		T2	2		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140815

1

T1

3

T3

10

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	849	1			T3	1		T5	10		T21	1
valid_sources[0x01]	526	1			T5	14		T9	3		T23	4
valid_sources[0x02]	504	1			T5	14		T8	1		T9	2
valid_sources[0x03]	450	1			T5	17		T9	1		T23	3
valid_sources[0x04]	738	1			T5	9		T9	1		T60	1
valid_sources[0x05]	530	1			T5	12		T9	1		T65	1
valid_sources[0x06]	864	1			T5	14		T20	96		T9	1
valid_sources[0x07]	622	1			T5	6		T21	2		T9	5
valid_sources[0x08]	574	1			T5	18		T8	1		T14	1
valid_sources[0x09]	736	1			T5	8		T21	28		T9	5
valid_sources[0x0a]	475	1			T5	11		T23	7		T50	3
valid_sources[0x0b]	539	1			T5	13		T71	2		T65	2
valid_sources[0x0c]	764	1			T5	10		T39	1		T21	13
valid_sources[0x0d]	465	1			T5	7		T23	3		T50	5
valid_sources[0x0e]	716	1			T5	13		T8	1		T23	10
valid_sources[0x0f]	702	1			T5	11		T8	1		T60	1
valid_sources[0x10]	540	1			T5	3		T9	1		T15	4
valid_sources[0x11]	773	1			T5	12		T14	1		T9	2
valid_sources[0x12]	494	1			T5	7		T21	3		T25	1
valid_sources[0x13]	497	1			T5	8		T21	2		T9	3
valid_sources[0x14]	543	1			T5	7		T8	1		T9	2
valid_sources[0x15]	1102	1			T5	14		T21	1		T9	3
valid_sources[0x16]	528	1			T5	14		T8	1		T9	3
valid_sources[0x17]	545	1			T3	1		T5	6		T64	1
valid_sources[0x18]	532	1			T5	12		T64	1		T65	1
valid_sources[0x19]	813	1			T5	12		T39	2		T23	3
valid_sources[0x1a]	597	1			T5	7		T8	1		T137	2
valid_sources[0x1b]	876	1			T5	14		T9	3		T64	2
valid_sources[0x1c]	831	1			T5	7		T8	1		T9	2
valid_sources[0x1d]	558	1			T5	15		T9	2		T60	1
valid_sources[0x1e]	604	1			T5	4		T9	1		T23	8
valid_sources[0x1f]	655	1			T5	14		T8	1		T21	1
valid_sources[0x20]	497	1			T5	11		T8	1		T21	2
valid_sources[0x21]	774	1			T5	16		T8	1		T54	1
valid_sources[0x22]	621	1			T5	11		T23	10		T50	19
valid_sources[0x23]	737	1			T3	3		T5	4		T9	6
valid_sources[0x24]	551	1			T5	7		T8	1		T9	3
valid_sources[0x25]	687	1			T5	10		T21	1		T9	1
valid_sources[0x26]	653	1			T5	12		T9	1		T60	7
valid_sources[0x27]	857	1			T5	9		T65	2		T23	15
valid_sources[0x28]	616	1			T5	13		T8	1		T9	5
valid_sources[0x29]	527	1			T5	9		T8	1		T21	1
valid_sources[0x2a]	830	1			T5	6		T8	2		T9	1
valid_sources[0x2b]	630	1			T5	8		T9	1		T60	5
valid_sources[0x2c]	601	1			T5	13		T19	2		T8	2
valid_sources[0x2d]	429	1			T5	9		T9	2		T64	1
valid_sources[0x2e]	834	1			T5	7		T11	1		T23	12
valid_sources[0x2f]	909	1			T5	14		T65	2		T23	3
valid_sources[0x30]	467	1			T5	13		T8	1		T23	5
valid_sources[0x31]	628	1			T5	13		T9	2		T60	1
valid_sources[0x32]	731	1			T5	8		T9	5		T60	2
valid_sources[0x33]	490	1			T5	8		T21	3		T9	2
valid_sources[0x34]	509	1			T5	10		T9	1		T131	4
valid_sources[0x35]	491	1			T5	12		T23	12		T50	8
valid_sources[0x36]	486	1			T5	10		T9	3		T23	3
valid_sources[0x37]	720	1			T5	8		T8	1		T9	2
valid_sources[0x38]	1001	1			T5	4		T9	2		T23	10
valid_sources[0x39]	702	1			T5	16		T8	1		T9	1
valid_sources[0x3a]	620	1			T5	7		T64	1		T23	10
valid_sources[0x3b]	429	1			T5	10		T21	1		T9	1
valid_sources[0x3c]	712	1			T5	12		T9	6		T23	5
valid_sources[0x3d]	514	1			T5	8		T72	3		T9	1
valid_sources[0x3e]	991	1			T5	7		T21	147		T64	2
valid_sources[0x3f]	752	1			T5	12		T40	9		T60	1
valid_sources[0x40]	708	1			T5	13		T8	3		T9	2
valid_sources[0x41]	527	1			T5	12		T9	3		T64	3
valid_sources[0x42]	536	1			T5	11		T64	1		T23	5
valid_sources[0x43]	498	1			T5	12		T9	2		T23	5
valid_sources[0x44]	533	1			T5	11		T38	1		T23	12
valid_sources[0x45]	624	1			T5	11		T9	1		T60	11
valid_sources[0x46]	866	1			T5	9		T19	2		T23	21
valid_sources[0x47]	674	1			T5	4		T6	2		T9	4
valid_sources[0x48]	602	1			T5	5		T9	2		T60	8
valid_sources[0x49]	786	1			T5	14		T8	1		T21	121
valid_sources[0x4a]	685	1			T5	13		T8	1		T9	1
valid_sources[0x4b]	641	1			T5	8		T54	1		T23	4
valid_sources[0x4c]	749	1			T5	11		T12	2		T60	2
valid_sources[0x4d]	815	1			T5	10		T8	1		T9	3
valid_sources[0x4e]	485	1			T5	8		T8	1		T9	5
valid_sources[0x4f]	1056	1			T5	8		T39	1		T21	143
valid_sources[0x50]	888	1			T5	14		T22	40		T23	14
valid_sources[0x51]	626	1			T5	17		T65	2		T23	8
valid_sources[0x52]	645	1			T5	7		T40	23		T9	1
valid_sources[0x53]	634	1			T5	4		T53	2		T9	1
valid_sources[0x54]	576	1			T5	12		T23	2		T50	9
valid_sources[0x55]	765	1			T5	14		T9	1		T23	2
valid_sources[0x56]	743	1			T5	9		T8	1		T23	10
valid_sources[0x57]	1011	1			T5	8		T23	7		T50	1
valid_sources[0x58]	553	1			T5	10		T8	1		T9	1
valid_sources[0x59]	621	1			T5	11		T9	3		T15	1
valid_sources[0x5a]	777	1			T4	3		T5	4		T97	6
valid_sources[0x5b]	589	1			T5	8		T8	1		T21	3
valid_sources[0x5c]	498	1			T5	11		T8	1		T64	1
valid_sources[0x5d]	614	1			T5	14		T9	2		T23	9
valid_sources[0x5e]	534	1			T5	12		T9	3		T60	1
valid_sources[0x5f]	855	1			T5	9		T9	3		T64	1
valid_sources[0x60]	649	1			T5	10		T8	2		T60	3
valid_sources[0x61]	712	1			T5	12		T60	1		T23	12
valid_sources[0x62]	673	1			T5	12		T23	4		T50	5
valid_sources[0x63]	791	1			T5	9		T8	1		T9	4
valid_sources[0x64]	858	1			T5	9		T9	6		T64	1
valid_sources[0x65]	598	1			T5	7		T38	1		T9	1
valid_sources[0x66]	928	1			T5	9		T21	193		T9	1
valid_sources[0x67]	601	1			T5	9		T9	4		T23	1
valid_sources[0x68]	790	1			T5	7		T9	6		T50	9
valid_sources[0x69]	464	1			T5	11		T7	2		T60	1
valid_sources[0x6a]	688	1			T5	12		T8	1		T9	3
valid_sources[0x6b]	645	1			T3	1		T5	7		T9	1
valid_sources[0x6c]	511	1			T5	11		T9	1		T23	11
valid_sources[0x6d]	696	1			T5	15		T8	1		T21	1
valid_sources[0x6e]	709	1			T5	13		T23	10		T50	44
valid_sources[0x6f]	529	1			T5	10		T8	1		T9	1
valid_sources[0x70]	752	1			T5	11		T9	2		T23	20
valid_sources[0x71]	438	1			T5	6		T8	1		T14	1
valid_sources[0x72]	806	1			T5	8		T23	4		T50	35
valid_sources[0x73]	788	1			T5	11		T8	1		T14	1
valid_sources[0x74]	940	1			T5	19		T9	4		T23	7
valid_sources[0x75]	619	1			T5	13		T19	3		T39	3
valid_sources[0x76]	591	1			T5	6		T9	1		T138	1
valid_sources[0x77]	605	1			T5	8		T8	1		T52	1
valid_sources[0x78]	633	1			T5	6		T50	27		T47	8
valid_sources[0x79]	515	1			T5	3		T23	4		T50	6
valid_sources[0x7a]	965	1			T5	14		T8	1		T23	15
valid_sources[0x7b]	597	1			T5	8		T8	1		T9	1
valid_sources[0x7c]	677	1			T5	14		T9	3		T64	1
valid_sources[0x7d]	537	1			T5	11		T8	1		T9	4
valid_sources[0x7e]	646	1			T5	10		T39	1		T8	2
valid_sources[0x7f]	714	1			T5	14		T9	1		T60	1
valid_sources[0x80]	903	1			T5	11		T9	1		T23	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36237

1

T5

673

T22

4

T20

8

values[0x0]

all_enables

biggest_size

49136

1

T1

2

T3

3

T4

1

values[0x1]

all_enables

biggest_size

47038

1

T3

2

T5

890

T22

5