Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14116789

1

T3

12988

T4

24674

T5

3508

full_word

54044047

1

T1

18432

T2

10000

T3

130514

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68160536	1			T1	18432		T2	10000		T3	143502
auto[TlIntgErrCmd]	102	1			T57	3		T58	6		T59	4
auto[TlIntgErrData]	92	1			T57	5		T58	6		T59	3
auto[TlIntgErrBoth]	106	1			T57	2		T58	8		T59	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31239467

1

T1

9216

T2

4980

T3

53733

auto[1]

36921369

1

T1

9216

T2

5020

T3

89769

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6754483	1			T3	4871		T4	12400		T5	823
auto[TlIntgErrNone]	partial	auto[1]	7362046	1			T3	8117		T4	12274		T5	2685
auto[TlIntgErrNone]	full_word	auto[0]	24484830	1			T1	9216		T2	4980		T3	48862
auto[TlIntgErrNone]	full_word	auto[1]	29559177	1			T1	9216		T2	5020		T3	81652
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T57	2		T58	3		T59	3
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T58	1		T59	1		T123	2
auto[TlIntgErrCmd]	full_word	auto[0]	10	1			T57	1		T58	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T57	2		T58	3		T59	2
auto[TlIntgErrData]	partial	auto[1]	37	1			T57	3		T58	2		T59	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T122	1		T127	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T58	1		T121	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T57	1		T58	2		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T57	1		T58	5		T59	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T58	1		T123	1		T121	2
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T130	1		T128	1		-	-