Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	667897	1			T5	3		T7	55		T22	12
auto[1]	11125656	1			T2	4980		T3	4918		T4	114275
auto[2]	536335	1			T5	2		T7	44		T22	18
auto[3]	11002552	1			T2	5019		T3	4793		T4	113294

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15065109	1			T2	9999		T3	8122		T4	188005
auto[1]	2230032	1			T3	755		T4	18871		T5	13
auto[2]	2238448	1			T3	769		T4	18804		T5	16
auto[3]	3798851	1			T3	65		T4	1889		T5	2

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8941857

1

T2

9987

T3

9704

T5

103

auto[1]

14390583

1

T2

12

T3

7

T4

227569

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	187315	1			T5	3		T22	8		T20	9
auto[0]	auto[0]	auto[1]	19278	1			T22	2		T20	3		T8	2
auto[0]	auto[0]	auto[2]	19301	1			T22	2		T20	1		T8	2
auto[0]	auto[0]	auto[3]	7350	1			T7	55		T72	59		T38	408
auto[0]	auto[1]	auto[0]	3504518	1			T2	4972		T3	4095		T5	33
auto[0]	auto[1]	auto[1]	352489	1			T3	380		T5	6		T12	406
auto[0]	auto[1]	auto[2]	351306	1			T3	402		T5	5		T12	407
auto[0]	auto[1]	auto[3]	66046	1			T3	36		T5	2		T12	88
auto[0]	auto[2]	auto[0]	154348	1			T8	26		T38	22		T60	1970
auto[0]	auto[2]	auto[1]	15915	1			T8	4		T38	82		T60	180
auto[0]	auto[2]	auto[2]	19599	1			T5	2		T22	17		T20	18
auto[0]	auto[2]	auto[3]	5972	1			T7	44		T22	1		T72	42
auto[0]	auto[3]	auto[0]	3467104	1			T2	5015		T3	4021		T5	36
auto[0]	auto[3]	auto[1]	349037	1			T3	374		T5	7		T12	408
auto[0]	auto[3]	auto[2]	354204	1			T3	367		T5	9		T12	408
auto[0]	auto[3]	auto[3]	68075	1			T3	29		T12	86		T6	2
auto[1]	auto[0]	auto[0]	14677	1			T97	204		T60	2		T100	641
auto[1]	auto[0]	auto[1]	64476	1			T97	806		T100	2750		T102	3273
auto[1]	auto[0]	auto[2]	64620	1			T97	904		T100	2820		T102	3274
auto[1]	auto[0]	auto[3]	290880	1			T72	2		T97	3766		T100	12348
auto[1]	auto[1]	auto[0]	3863485	1			T2	8		T3	4		T4	94437
auto[1]	auto[1]	auto[1]	707903	1			T3	1		T4	9416		T12	1
auto[1]	auto[1]	auto[2]	685208	1			T4	9432		T12	2		T40	4
auto[1]	auto[1]	auto[3]	1594701	1			T4	990		T53	2		T40	1
auto[1]	auto[2]	auto[0]	10977	1			T60	4		T100	615		T102	656
auto[1]	auto[2]	auto[1]	49254	1			T100	2575		T102	2999		T136	4542
auto[1]	auto[2]	auto[2]	50908	1			T97	767		T100	1800		T102	2223
auto[1]	auto[2]	auto[3]	229362	1			T97	3323		T100	8514		T102	9811
auto[1]	auto[3]	auto[0]	3862685	1			T2	4		T3	2		T4	93568
auto[1]	auto[3]	auto[1]	671680	1			T4	9455		T39	2		T40	11
auto[1]	auto[3]	auto[2]	693302	1			T4	9372		T53	2		T40	7
auto[1]	auto[3]	auto[3]	1536465	1			T4	899		T53	3		T40	2