Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	290489578	193906	0	0
ctrl_regwen_rd_A	290489578	4143	0	0
exec_rd_A	290489578	3875	0	0
exec_regwen_rd_A	290489578	3876	0	0
readback_rd_A	290489578	2580	0	0
readback_regwen_rd_A	290489578	1989	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290489578	193906	0	0
T5	108519	2680	0	0
T6	3762	0	0	0
T7	9155	0	0	0
T11	665	0	0	0
T12	9581	0	0	0
T13	6774	0	0	0
T19	194965	0	0	0
T21	0	1532	0	0
T22	694349	0	0	0
T23	0	4141	0	0
T24	1651	0	0	0
T39	121731	0	0	0
T47	0	5695	0	0
T50	0	4595	0	0
T51	0	6548	0	0
T55	0	12603	0	0
T66	0	4674	0	0
T67	0	1900	0	0
T68	0	910	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290489578	4143	0	0
T46	0	491	0	0
T49	65898	0	0	0
T61	0	74	0	0
T68	51989	89	0	0
T87	304604	0	0	0
T102	147199	0	0	0
T105	0	443	0	0
T106	0	48	0	0
T107	0	153	0	0
T108	0	414	0	0
T109	0	327	0	0
T110	0	105	0	0
T111	0	167	0	0
T112	50276	0	0	0
T113	3842	0	0	0
T114	12685	0	0	0
T115	146137	0	0	0
T116	6609	0	0	0
T117	444029	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290489578	3875	0	0
T46	0	469	0	0
T49	65898	0	0	0
T61	0	31	0	0
T68	51989	78	0	0
T87	304604	0	0	0
T102	147199	0	0	0
T105	0	454	0	0
T106	0	48	0	0
T107	0	171	0	0
T108	0	384	0	0
T109	0	380	0	0
T110	0	137	0	0
T111	0	144	0	0
T112	50276	0	0	0
T113	3842	0	0	0
T114	12685	0	0	0
T115	146137	0	0	0
T116	6609	0	0	0
T117	444029	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290489578	3876	0	0
T46	0	476	0	0
T49	65898	0	0	0
T61	0	25	0	0
T68	51989	75	0	0
T87	304604	0	0	0
T102	147199	0	0	0
T105	0	443	0	0
T106	0	79	0	0
T107	0	122	0	0
T108	0	339	0	0
T109	0	409	0	0
T110	0	146	0	0
T111	0	185	0	0
T112	50276	0	0	0
T113	3842	0	0	0
T114	12685	0	0	0
T115	146137	0	0	0
T116	6609	0	0	0
T117	444029	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290489578	2580	0	0
T46	0	491	0	0
T49	65898	0	0	0
T68	51989	62	0	0
T87	304604	0	0	0
T102	147199	0	0	0
T105	0	523	0	0
T106	0	71	0	0
T107	0	127	0	0
T108	0	475	0	0
T109	0	280	0	0
T110	0	99	0	0
T111	0	211	0	0
T112	50276	0	0	0
T113	3842	0	0	0
T114	12685	0	0	0
T115	146137	0	0	0
T116	6609	0	0	0
T117	444029	0	0	0
T118	0	50	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290489578	1989	0	0
T46	0	366	0	0
T49	65898	0	0	0
T68	51989	53	0	0
T87	304604	0	0	0
T102	147199	0	0	0
T105	0	353	0	0
T106	0	50	0	0
T107	0	188	0	0
T108	0	299	0	0
T109	0	253	0	0
T110	0	82	0	0
T111	0	142	0	0
T112	50276	0	0	0
T113	3842	0	0	0
T114	12685	0	0	0
T115	146137	0	0	0
T116	6609	0	0	0
T117	444029	0	0	0
T118	0	49	0	0