Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13750651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58676027

1

T1

485413

T2

264426

T3

8877

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36104682	1			T1	264998		T2	145163		T3	4836
values[0x0]	16788555	1			T1	128387		T2	70303		T3	2337
values[0x1]	19533441	1			T1	136687		T2	75395		T3	2547

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6849758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65576920

1

T1

507901

T2

277692

T3

9303

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	295252	1			T1	1986		T2	1212		T3	38
valid_sources[0x01]	335894	1			T1	2116		T2	1201		T3	49
valid_sources[0x02]	329705	1			T1	1972		T2	1131		T3	32
valid_sources[0x03]	334252	1			T1	2075		T2	1235		T3	54
valid_sources[0x04]	262301	1			T1	2126		T2	1102		T3	22
valid_sources[0x05]	297105	1			T1	1990		T2	1173		T3	3
valid_sources[0x06]	269030	1			T1	2116		T2	1105		T3	30
valid_sources[0x07]	249372	1			T1	2035		T2	1092		T3	38
valid_sources[0x08]	373793	1			T1	2052		T2	1097		T3	23
valid_sources[0x09]	301705	1			T1	1945		T2	1126		T3	25
valid_sources[0x0a]	261284	1			T1	2102		T2	1108		T3	30
valid_sources[0x0b]	286885	1			T1	2026		T2	1200		T3	26
valid_sources[0x0c]	284945	1			T1	1957		T2	1144		T3	28
valid_sources[0x0d]	295624	1			T1	2126		T2	1124		T3	10
valid_sources[0x0e]	274784	1			T1	2054		T2	1253		T3	34
valid_sources[0x0f]	251423	1			T1	2168		T2	1205		T3	16
valid_sources[0x10]	290345	1			T1	2159		T2	1100		T3	64
valid_sources[0x11]	256135	1			T1	2208		T2	1115		T3	47
valid_sources[0x12]	274959	1			T1	2131		T2	1112		T3	61
valid_sources[0x13]	255137	1			T1	2007		T2	1193		T3	70
valid_sources[0x14]	262844	1			T1	2043		T2	1152		T3	34
valid_sources[0x15]	259406	1			T1	2040		T2	1133		T3	62
valid_sources[0x16]	292287	1			T1	2100		T2	973		T3	65
valid_sources[0x17]	284050	1			T1	1995		T2	1220		T3	96
valid_sources[0x18]	289170	1			T1	2039		T2	1136		T3	61
valid_sources[0x19]	295312	1			T1	2155		T2	1078		T3	75
valid_sources[0x1a]	255212	1			T1	2082		T2	1171		T3	27
valid_sources[0x1b]	300772	1			T1	2069		T2	1120		T3	41
valid_sources[0x1c]	266169	1			T1	2064		T2	1115		T3	37
valid_sources[0x1d]	307009	1			T1	2119		T2	1186		T3	33
valid_sources[0x1e]	310543	1			T1	2140		T2	1140		T3	50
valid_sources[0x1f]	274994	1			T1	2089		T2	1166		T3	45
valid_sources[0x20]	266020	1			T1	1941		T2	1255		T3	70
valid_sources[0x21]	304628	1			T1	1972		T2	1141		T3	54
valid_sources[0x22]	292279	1			T1	1997		T2	1107		T3	43
valid_sources[0x23]	332081	1			T1	2188		T2	1154		T3	37
valid_sources[0x24]	287544	1			T1	2018		T2	1190		T3	19
valid_sources[0x25]	276717	1			T1	2023		T2	1159		T3	40
valid_sources[0x26]	267198	1			T1	1977		T2	1155		T3	64
valid_sources[0x27]	305477	1			T1	2100		T2	1157		T3	41
valid_sources[0x28]	312264	1			T1	2163		T2	1080		T3	19
valid_sources[0x29]	292348	1			T1	2019		T2	1059		T3	84
valid_sources[0x2a]	265150	1			T1	2114		T2	1178		T3	50
valid_sources[0x2b]	265592	1			T1	2046		T2	1155		T3	8
valid_sources[0x2c]	260111	1			T1	2104		T2	1276		T3	37
valid_sources[0x2d]	338970	1			T1	2161		T2	1258		T3	48
valid_sources[0x2e]	298511	1			T1	2066		T2	1220		T3	19
valid_sources[0x2f]	275694	1			T1	2011		T2	1175		T3	17
valid_sources[0x30]	294974	1			T1	2012		T2	1101		T3	18
valid_sources[0x31]	288168	1			T1	2212		T2	1216		T3	23
valid_sources[0x32]	256313	1			T1	1903		T2	1221		T3	39
valid_sources[0x33]	257512	1			T1	2081		T2	1232		T3	19
valid_sources[0x34]	263801	1			T1	2089		T2	1111		T3	2
valid_sources[0x35]	265663	1			T1	2091		T2	1083		T3	46
valid_sources[0x36]	285476	1			T1	2066		T2	1072		T3	52
valid_sources[0x37]	282581	1			T1	2084		T2	1140		T3	33
valid_sources[0x38]	282299	1			T1	2092		T2	1099		T3	39
valid_sources[0x39]	274976	1			T1	2022		T2	1130		T3	11
valid_sources[0x3a]	302238	1			T1	2048		T2	1183		T3	24
valid_sources[0x3b]	281810	1			T1	2131		T2	1179		T3	42
valid_sources[0x3c]	302589	1			T1	2038		T2	1085		T3	16
valid_sources[0x3d]	259568	1			T1	2051		T2	1138		T3	10
valid_sources[0x3e]	253231	1			T1	2070		T2	1118		T3	35
valid_sources[0x3f]	255410	1			T1	2050		T2	1073		T3	29
valid_sources[0x40]	258567	1			T1	2133		T2	1133		T3	46
valid_sources[0x41]	299266	1			T1	2063		T2	1125		T3	59
valid_sources[0x42]	281658	1			T1	2034		T2	1210		T3	72
valid_sources[0x43]	275932	1			T1	2067		T2	1026		T3	14
valid_sources[0x44]	342947	1			T1	2149		T2	1119		T3	24
valid_sources[0x45]	322475	1			T1	2128		T2	1190		T3	75
valid_sources[0x46]	355775	1			T1	2110		T2	1137		T3	40
valid_sources[0x47]	269742	1			T1	2044		T2	1088		T3	31
valid_sources[0x48]	270769	1			T1	2060		T2	1062		T3	21
valid_sources[0x49]	279781	1			T1	2155		T2	1103		T3	37
valid_sources[0x4a]	334105	1			T1	2165		T2	1118		T3	39
valid_sources[0x4b]	406633	1			T1	2007		T2	1128		T3	23
valid_sources[0x4c]	280432	1			T1	2034		T2	1163		T3	7
valid_sources[0x4d]	305512	1			T1	1978		T2	1088		T3	41
valid_sources[0x4e]	256741	1			T1	2081		T2	1066		T3	37
valid_sources[0x4f]	280342	1			T1	2081		T2	1232		T3	34
valid_sources[0x50]	261978	1			T1	2010		T2	1117		T3	22
valid_sources[0x51]	296002	1			T1	2038		T2	1160		T3	69
valid_sources[0x52]	251934	1			T1	2054		T2	1106		T3	24
valid_sources[0x53]	252607	1			T1	2077		T2	1186		T3	18
valid_sources[0x54]	298518	1			T1	2069		T2	1114		T3	77
valid_sources[0x55]	343523	1			T1	2016		T2	1099		T3	57
valid_sources[0x56]	287662	1			T1	2104		T2	1184		T3	33
valid_sources[0x57]	269936	1			T1	2095		T2	1275		T3	46
valid_sources[0x58]	252888	1			T1	2056		T2	1101		T3	40
valid_sources[0x59]	258455	1			T1	2072		T2	1062		T3	36
valid_sources[0x5a]	259446	1			T1	2009		T2	1183		T3	46
valid_sources[0x5b]	291189	1			T1	2011		T2	1102		T3	38
valid_sources[0x5c]	286956	1			T1	2135		T2	1064		T3	18
valid_sources[0x5d]	260050	1			T1	2065		T2	1157		T3	69
valid_sources[0x5e]	265624	1			T1	2028		T2	1067		T3	12
valid_sources[0x5f]	253057	1			T1	2128		T2	1114		T3	87
valid_sources[0x60]	250716	1			T1	2131		T2	1136		T3	27
valid_sources[0x61]	260383	1			T1	2009		T2	1232		T3	16
valid_sources[0x62]	271308	1			T1	2125		T2	1104		T3	15
valid_sources[0x63]	308981	1			T1	2111		T2	1243		T3	71
valid_sources[0x64]	268460	1			T1	2022		T2	1195		T3	60
valid_sources[0x65]	303477	1			T1	1995		T2	1133		T3	40
valid_sources[0x66]	275566	1			T1	2008		T2	1102		T3	84
valid_sources[0x67]	262792	1			T1	1993		T2	1090		T3	60
valid_sources[0x68]	281879	1			T1	2123		T2	1122		T3	4
valid_sources[0x69]	281979	1			T1	2057		T2	1189		T3	63
valid_sources[0x6a]	268257	1			T1	2127		T2	1054		T3	54
valid_sources[0x6b]	265077	1			T1	2094		T2	1066		T3	48
valid_sources[0x6c]	297420	1			T1	2064		T2	1220		T3	19
valid_sources[0x6d]	295247	1			T1	2117		T2	1093		T3	47
valid_sources[0x6e]	249523	1			T1	2048		T2	1158		T3	52
valid_sources[0x6f]	265902	1			T1	2145		T2	1102		T3	34
valid_sources[0x70]	273109	1			T1	2157		T2	1088		T3	36
valid_sources[0x71]	296527	1			T1	2157		T2	1167		T3	45
valid_sources[0x72]	257851	1			T1	2094		T2	1178		T3	15
valid_sources[0x73]	279322	1			T1	1995		T2	1172		T3	74
valid_sources[0x74]	281849	1			T1	2052		T2	1183		T3	30
valid_sources[0x75]	327541	1			T1	2036		T2	1202		T3	20
valid_sources[0x76]	354279	1			T1	2059		T2	1211		T3	22
valid_sources[0x77]	266552	1			T1	2107		T2	1214		T3	45
valid_sources[0x78]	264893	1			T1	2061		T2	1162		T3	57
valid_sources[0x79]	286495	1			T1	2009		T2	1112		T3	21
valid_sources[0x7a]	277419	1			T1	2058		T2	1203		T3	25
valid_sources[0x7b]	320067	1			T1	2114		T2	1103		T3	60
valid_sources[0x7c]	275419	1			T1	2061		T2	1232		T3	26
valid_sources[0x7d]	268064	1			T1	2109		T2	1173		T3	64
valid_sources[0x7e]	257493	1			T1	2048		T2	1076		T3	18
valid_sources[0x7f]	262866	1			T1	2041		T2	1228		T3	36
valid_sources[0x80]	251837	1			T1	1982		T2	1194		T3	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29232594

1

T1

242635

T2

132021

T3

4401

values[0x0]

all_enables

biggest_size

14723195

1

T1

121683

T2

66173

T3

2219

values[0x1]

all_enables

biggest_size

14720238

1

T1

121095

T2

66232

T3

2257

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

126557

1

T1

64

T2

2

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48272	1			T1	31		T6	26		T21	18
values[0x0]	55345	1			T1	88		T2	5		T3	1
values[0x1]	59797	1			T1	86		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

135470

1

T1

79

T2

2

T8

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	618	1			T25	19		T54	1		T128	1
valid_sources[0x01]	756	1			T24	6		T25	17		T54	42
valid_sources[0x02]	617	1			T21	2		T18	1		T25	14
valid_sources[0x03]	805	1			T12	2		T18	2		T25	23
valid_sources[0x04]	802	1			T18	275		T24	38		T25	23
valid_sources[0x05]	759	1			T25	20		T54	111		T45	12
valid_sources[0x06]	594	1			T18	5		T62	1		T25	22
valid_sources[0x07]	696	1			T21	10		T18	168		T25	21
valid_sources[0x08]	467	1			T21	2		T25	22		T45	2
valid_sources[0x09]	491	1			T18	1		T25	19		T73	27
valid_sources[0x0a]	472	1			T18	1		T25	13		T19	1
valid_sources[0x0b]	481	1			T17	3		T25	18		T54	22
valid_sources[0x0c]	1094	1			T4	1		T23	1		T62	2
valid_sources[0x0d]	685	1			T18	1		T24	71		T25	18
valid_sources[0x0e]	518	1			T25	20		T102	1		T45	8
valid_sources[0x0f]	569	1			T24	82		T25	18		T54	1
valid_sources[0x10]	832	1			T25	10		T54	75		T45	8
valid_sources[0x11]	615	1			T18	1		T24	1		T25	24
valid_sources[0x12]	663	1			T18	56		T24	1		T25	17
valid_sources[0x13]	641	1			T24	51		T25	11		T54	1
valid_sources[0x14]	714	1			T24	8		T25	19		T102	1
valid_sources[0x15]	486	1			T25	11		T42	1		T45	2
valid_sources[0x16]	901	1			T18	1		T24	1		T25	17
valid_sources[0x17]	1088	1			T21	4		T24	84		T25	13
valid_sources[0x18]	603	1			T25	16		T54	1		T42	1
valid_sources[0x19]	761	1			T18	2		T25	20		T19	2
valid_sources[0x1a]	497	1			T21	2		T18	2		T24	19
valid_sources[0x1b]	539	1			T25	32		T129	2		T45	4
valid_sources[0x1c]	817	1			T21	2		T18	150		T24	1
valid_sources[0x1d]	709	1			T25	18		T19	2		T45	6
valid_sources[0x1e]	417	1			T18	2		T7	4		T25	20
valid_sources[0x1f]	758	1			T10	1		T25	16		T54	2
valid_sources[0x20]	561	1			T25	13		T54	2		T19	2
valid_sources[0x21]	568	1			T18	1		T24	4		T25	16
valid_sources[0x22]	761	1			T24	180		T25	19		T54	3
valid_sources[0x23]	544	1			T24	18		T25	15		T130	1
valid_sources[0x24]	637	1			T17	2		T24	1		T25	17
valid_sources[0x25]	615	1			T18	5		T25	16		T54	1
valid_sources[0x26]	935	1			T21	2		T24	1		T60	1
valid_sources[0x27]	439	1			T25	13		T45	11		T43	1
valid_sources[0x28]	740	1			T21	1		T18	1		T24	1
valid_sources[0x29]	562	1			T24	1		T25	24		T128	1
valid_sources[0x2a]	679	1			T3	2		T18	1		T25	22
valid_sources[0x2b]	527	1			T24	3		T25	28		T54	6
valid_sources[0x2c]	580	1			T6	53		T24	1		T25	20
valid_sources[0x2d]	483	1			T24	3		T25	23		T129	1
valid_sources[0x2e]	596	1			T10	2		T24	124		T25	24
valid_sources[0x2f]	512	1			T18	6		T25	18		T54	1
valid_sources[0x30]	579	1			T18	3		T25	20		T54	105
valid_sources[0x31]	661	1			T18	1		T24	1		T25	15
valid_sources[0x32]	653	1			T1	205		T10	1		T25	21
valid_sources[0x33]	624	1			T24	10		T25	18		T19	1
valid_sources[0x34]	707	1			T24	74		T25	27		T45	1
valid_sources[0x35]	627	1			T8	8		T25	17		T45	20
valid_sources[0x36]	510	1			T24	1		T25	21		T54	3
valid_sources[0x37]	549	1			T25	22		T54	2		T45	3
valid_sources[0x38]	575	1			T24	4		T25	21		T125	2
valid_sources[0x39]	651	1			T25	14		T42	1		T45	15
valid_sources[0x3a]	599	1			T21	18		T24	1		T25	14
valid_sources[0x3b]	507	1			T25	22		T42	1		T45	1
valid_sources[0x3c]	718	1			T24	138		T25	20		T54	1
valid_sources[0x3d]	486	1			T25	14		T128	1		T45	4
valid_sources[0x3e]	486	1			T25	25		T54	4		T19	2
valid_sources[0x3f]	571	1			T5	3		T18	4		T7	8
valid_sources[0x40]	747	1			T25	21		T54	3		T45	1
valid_sources[0x41]	493	1			T24	1		T25	15		T42	1
valid_sources[0x42]	629	1			T12	1		T24	120		T25	16
valid_sources[0x43]	567	1			T18	2		T24	1		T25	15
valid_sources[0x44]	671	1			T25	15		T131	3		T49	1
valid_sources[0x45]	412	1			T24	1		T25	9		T54	2
valid_sources[0x46]	879	1			T24	4		T25	18		T125	1
valid_sources[0x47]	509	1			T21	1		T25	20		T54	3
valid_sources[0x48]	870	1			T24	67		T25	23		T45	4
valid_sources[0x49]	468	1			T18	1		T24	3		T25	22
valid_sources[0x4a]	492	1			T24	1		T7	1		T25	19
valid_sources[0x4b]	708	1			T24	30		T25	24		T54	2
valid_sources[0x4c]	509	1			T12	2		T21	3		T7	6
valid_sources[0x4d]	473	1			T25	15		T125	1		T54	63
valid_sources[0x4e]	1004	1			T25	18		T132	1		T54	126
valid_sources[0x4f]	472	1			T24	2		T25	17		T54	1
valid_sources[0x50]	448	1			T24	1		T25	23		T42	1
valid_sources[0x51]	607	1			T25	10		T54	64		T45	8
valid_sources[0x52]	622	1			T18	1		T58	1		T24	1
valid_sources[0x53]	573	1			T18	3		T25	29		T54	46
valid_sources[0x54]	774	1			T24	3		T25	19		T54	3
valid_sources[0x55]	556	1			T25	18		T54	1		T42	1
valid_sources[0x56]	662	1			T25	19		T42	1		T45	1
valid_sources[0x57]	554	1			T24	62		T7	13		T25	25
valid_sources[0x58]	1000	1			T25	22		T42	1		T19	11
valid_sources[0x59]	563	1			T17	1		T24	2		T25	17
valid_sources[0x5a]	601	1			T25	20		T45	1		T43	1
valid_sources[0x5b]	783	1			T25	13		T54	1		T45	3
valid_sources[0x5c]	369	1			T25	16		T129	1		T46	5
valid_sources[0x5d]	578	1			T7	1		T25	16		T125	1
valid_sources[0x5e]	597	1			T25	25		T13	2		T45	15
valid_sources[0x5f]	568	1			T24	6		T25	20		T54	56
valid_sources[0x60]	872	1			T24	88		T25	21		T54	39
valid_sources[0x61]	541	1			T24	30		T60	1		T25	34
valid_sources[0x62]	618	1			T25	9		T125	1		T54	3
valid_sources[0x63]	692	1			T18	89		T25	19		T54	95
valid_sources[0x64]	689	1			T18	2		T25	14		T45	13
valid_sources[0x65]	767	1			T24	50		T25	5		T45	10
valid_sources[0x66]	717	1			T18	1		T24	146		T25	24
valid_sources[0x67]	623	1			T24	1		T25	15		T54	2
valid_sources[0x68]	837	1			T24	23		T7	2		T25	30
valid_sources[0x69]	510	1			T24	3		T25	15		T103	2
valid_sources[0x6a]	657	1			T21	1		T7	1		T25	21
valid_sources[0x6b]	563	1			T24	8		T25	26		T45	5
valid_sources[0x6c]	572	1			T60	1		T25	21		T54	3
valid_sources[0x6d]	1029	1			T17	2		T7	1		T25	23
valid_sources[0x6e]	614	1			T18	3		T24	122		T25	26
valid_sources[0x6f]	550	1			T18	6		T25	23		T54	4
valid_sources[0x70]	532	1			T18	1		T24	19		T25	17
valid_sources[0x71]	758	1			T24	3		T7	2		T25	13
valid_sources[0x72]	892	1			T12	1		T18	4		T25	18
valid_sources[0x73]	841	1			T25	18		T125	1		T45	14
valid_sources[0x74]	808	1			T12	1		T18	2		T25	11
valid_sources[0x75]	739	1			T17	3		T18	7		T24	170
valid_sources[0x76]	534	1			T21	4		T25	18		T125	1
valid_sources[0x77]	425	1			T24	1		T25	28		T45	4
valid_sources[0x78]	539	1			T25	20		T19	2		T46	14
valid_sources[0x79]	980	1			T24	1		T25	19		T54	1
valid_sources[0x7a]	574	1			T57	1		T25	16		T133	1
valid_sources[0x7b]	690	1			T11	8		T21	7		T18	24
valid_sources[0x7c]	588	1			T21	2		T25	21		T54	1
valid_sources[0x7d]	577	1			T4	1		T17	1		T25	27
valid_sources[0x7e]	858	1			T24	1		T26	44		T25	28
valid_sources[0x7f]	631	1			T24	1		T25	21		T45	6
valid_sources[0x80]	677	1			T24	87		T25	13		T132	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35340

1

T1

17

T6

12

T21

8

values[0x0]

all_enables

biggest_size

46766

1

T1

31

T2

2

T4

1

values[0x1]

all_enables

biggest_size

44451

1

T1

16

T8

3

T4

1