Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13376924

1

T1

37050

T2

26435

T3

843

full_word

53186835

1

T1

409589

T2

264426

T3

8877

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66563439	1			T1	446639		T2	290861		T3	9720
auto[TlIntgErrCmd]	104	1			T63	6		T64	7		T65	5
auto[TlIntgErrData]	111	1			T63	7		T64	7		T65	8
auto[TlIntgErrBoth]	105	1			T63	7		T64	6		T65	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30191661

1

T1

182506

T2

145163

T3

4836

auto[1]

36372098

1

T1

264133

T2

145698

T3

4884

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6366758	1			T1	14842		T2	13142		T3	435
auto[TlIntgErrNone]	partial	auto[1]	7009872	1			T1	22208		T2	13293		T3	408
auto[TlIntgErrNone]	full_word	auto[0]	23824753	1			T1	167664		T2	132021		T3	4401
auto[TlIntgErrNone]	full_word	auto[1]	29362056	1			T1	241925		T2	132405		T3	4476
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T63	3		T64	3		T65	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T63	3		T64	4		T65	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T117	1		T120	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T121	1		T122	2		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T63	3		T64	1		T65	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T63	3		T64	3		T65	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T65	1		T110	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T63	1		T64	3		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T63	2		T64	5		T65	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T63	5		T64	1		T65	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T123	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T115	1		T120	1		T119	1