Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	753086	1			T1	173		T4	25444		T5	48
auto[1]	10259029	1			T1	1916		T2	122247		T3	4836
auto[2]	617833	1			T1	116		T4	18384		T5	31
auto[3]	10134407	1			T1	1729		T2	122522		T3	4882

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13813477	1			T1	2838		T2	202366		T3	8103
auto[1]	2117910	1			T1	421		T2	20189		T3	772
auto[2]	2120281	1			T1	611		T2	20207		T3	790
auto[3]	3712687	1			T1	64		T2	2007		T3	53

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7948963

1

T1

3933

T3

9709

T5

449

auto[1]

13815392

1

T1

1

T2

244769

T3

9

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	312146	1			T1	136		T22	2818		T6	1
auto[0]	auto[0]	auto[1]	32329	1			T1	15		T22	303		T21	123
auto[0]	auto[0]	auto[2]	32388	1			T1	19		T22	281		T21	163
auto[0]	auto[0]	auto[3]	8691	1			T1	3		T5	48		T22	28
auto[0]	auto[1]	auto[0]	2971836	1			T1	1455		T3	4015		T10	12
auto[0]	auto[1]	auto[1]	312238	1			T1	289		T3	383		T5	3
auto[0]	auto[1]	auto[2]	295102	1			T1	145		T3	402		T5	6
auto[0]	auto[1]	auto[3]	57764	1			T1	27		T3	33		T5	164
auto[0]	auto[2]	auto[0]	269848	1			T22	2558		T21	913		T24	3
auto[0]	auto[2]	auto[1]	27849	1			T22	256		T21	88		T127	5
auto[0]	auto[2]	auto[2]	29619	1			T1	105		T5	1		T22	244
auto[0]	auto[2]	auto[3]	7331	1			T1	11		T5	30		T22	17
auto[0]	auto[3]	auto[0]	2932342	1			T1	1246		T3	4081		T10	22
auto[0]	auto[3]	auto[1]	290773	1			T1	117		T3	387		T5	5
auto[0]	auto[3]	auto[2]	309725	1			T1	342		T3	388		T5	17
auto[0]	auto[3]	auto[3]	58982	1			T1	23		T3	20		T5	175
auto[1]	auto[0]	auto[0]	12552	1			T4	864		T9	164		T22	2
auto[1]	auto[0]	auto[1]	54733	1			T4	3782		T9	757		T22	1
auto[1]	auto[0]	auto[2]	54259	1			T4	3788		T9	710		T62	4365
auto[1]	auto[0]	auto[3]	245988	1			T4	17010		T9	3238		T62	19448
auto[1]	auto[1]	auto[0]	3652766	1			T2	101171		T3	2		T4	142
auto[1]	auto[1]	auto[1]	688792	1			T2	10054		T3	1		T4	3803
auto[1]	auto[1]	auto[2]	680558	1			T2	10045		T4	647		T9	1350
auto[1]	auto[1]	auto[3]	1599973	1			T2	977		T4	17408		T5	1
auto[1]	auto[2]	auto[0]	9869	1			T4	834		T22	2		T21	2
auto[1]	auto[2]	auto[1]	42571	1			T4	3494		T62	3879		T36	967
auto[1]	auto[2]	auto[2]	42169	1			T4	2536		T9	675		T62	2890
auto[1]	auto[2]	auto[3]	188577	1			T4	11520		T9	2954		T62	12891
auto[1]	auto[3]	auto[0]	3652118	1			T1	1		T2	101195		T3	5
auto[1]	auto[3]	auto[1]	668625	1			T2	10135		T3	1		T4	381
auto[1]	auto[3]	auto[2]	676461	1			T2	10162		T4	2629		T9	2192
auto[1]	auto[3]	auto[3]	1545381	1			T2	1030		T4	11783		T9	9512