Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00



Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 5 5 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T6,T18 Yes T1,T2,T3 INPUT
oh_i[0] Yes Yes *T8,*T11,*T13 Yes T8,T11,T13 INPUT
oh_i[1] Unreachable Unreachable Unreachable INPUT
oh_i[8:2] Yes Yes T1,T21,T18 Yes T1,T21,T18 INPUT
addr_i[3:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT

*Tests covering at least one bit in the range