Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	319141387	189653	0	0
ctrl_regwen_rd_A	319141387	3828	0	0
exec_rd_A	319141387	3498	0	0
exec_regwen_rd_A	319141387	3697	0	0
readback_rd_A	319141387	2117	0	0
readback_regwen_rd_A	319141387	1756	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319141387	189653	0	0
T7	39213	0	0	0
T18	38972	2842	0	0
T24	182916	4893	0	0
T25	0	6081	0	0
T26	415680	0	0	0
T45	0	3250	0	0
T46	0	4076	0	0
T47	8833	0	0	0
T54	0	7828	0	0
T58	30248	0	0	0
T59	12608	0	0	0
T60	395557	0	0	0
T61	10373	0	0	0
T62	194571	0	0	0
T69	0	1171	0	0
T70	0	3078	0	0
T71	0	6070	0	0
T72	0	3463	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319141387	3828	0	0
T7	39213	0	0	0
T24	182916	376	0	0
T25	199088	487	0	0
T26	415680	0	0	0
T45	0	219	0	0
T47	8833	0	0	0
T50	22918	0	0	0
T59	12608	0	0	0
T60	395557	0	0	0
T61	10373	0	0	0
T62	194571	0	0	0
T70	0	175	0	0
T99	0	65	0	0
T105	0	234	0	0
T106	0	148	0	0
T107	0	331	0	0
T108	0	11	0	0
T109	0	49	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319141387	3498	0	0
T7	39213	0	0	0
T24	182916	275	0	0
T25	199088	474	0	0
T26	415680	0	0	0
T45	0	152	0	0
T47	8833	0	0	0
T50	22918	0	0	0
T59	12608	0	0	0
T60	395557	0	0	0
T61	10373	0	0	0
T62	194571	0	0	0
T70	0	152	0	0
T99	0	36	0	0
T105	0	238	0	0
T106	0	181	0	0
T107	0	369	0	0
T108	0	13	0	0
T109	0	8	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319141387	3697	0	0
T7	39213	0	0	0
T24	182916	376	0	0
T25	199088	463	0	0
T26	415680	0	0	0
T45	0	177	0	0
T47	8833	0	0	0
T50	22918	0	0	0
T59	12608	0	0	0
T60	395557	0	0	0
T61	10373	0	0	0
T62	194571	0	0	0
T70	0	167	0	0
T99	0	22	0	0
T105	0	263	0	0
T106	0	194	0	0
T107	0	364	0	0
T108	0	1	0	0
T109	0	15	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319141387	2117	0	0
T7	39213	0	0	0
T24	182916	289	0	0
T25	199088	453	0	0
T26	415680	0	0	0
T45	0	174	0	0
T47	8833	0	0	0
T50	22918	0	0	0
T59	12608	0	0	0
T60	395557	0	0	0
T61	10373	0	0	0
T62	194571	0	0	0
T70	0	179	0	0
T105	0	332	0	0
T106	0	155	0	0
T107	0	301	0	0
T109	0	50	0	0
T110	0	2	0	0
T111	0	38	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319141387	1756	0	0
T7	39213	0	0	0
T24	182916	250	0	0
T25	199088	459	0	0
T26	415680	0	0	0
T45	0	142	0	0
T47	8833	0	0	0
T50	22918	0	0	0
T59	12608	0	0	0
T60	395557	0	0	0
T61	10373	0	0	0
T62	194571	0	0	0
T70	0	172	0	0
T105	0	215	0	0
T106	0	111	0	0
T107	0	214	0	0
T109	0	35	0	0
T111	0	20	0	0
T112	0	21	0	0