Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14174728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59440717

1

T1

37364

T2

207593

T3

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36708336	1			T1	20649		T2	114011		T3	372
values[0x0]	17032113	1			T1	9880		T2	55180		T3	199
values[0x1]	19874996	1			T1	10792		T2	58938		T3	437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7063249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66552196

1

T1

39306

T2

217888

T3

476

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	274965	1			T2	1076		T3	2		T4	586
valid_sources[0x01]	243625	1			T2	967		T3	4		T4	546
valid_sources[0x02]	243028	1			T2	920		T3	1		T4	601
valid_sources[0x03]	301902	1			T2	822		T3	3		T4	600
valid_sources[0x04]	250910	1			T2	927		T3	2		T4	595
valid_sources[0x05]	276795	1			T2	1147		T3	7		T4	605
valid_sources[0x06]	283118	1			T2	801		T3	2		T4	583
valid_sources[0x07]	337794	1			T2	847		T3	6		T4	603
valid_sources[0x08]	303411	1			T2	615		T3	2		T4	566
valid_sources[0x09]	245565	1			T2	891		T3	4		T4	660
valid_sources[0x0a]	273296	1			T2	849		T3	2		T4	653
valid_sources[0x0b]	307940	1			T1	359		T2	1017		T3	6
valid_sources[0x0c]	296330	1			T2	893		T3	4		T4	559
valid_sources[0x0d]	328475	1			T2	1059		T3	2		T4	578
valid_sources[0x0e]	241218	1			T2	992		T3	5		T4	612
valid_sources[0x0f]	309557	1			T2	1133		T3	5		T4	635
valid_sources[0x10]	290123	1			T2	990		T3	5		T4	610
valid_sources[0x11]	275275	1			T2	936		T3	5		T4	690
valid_sources[0x12]	250364	1			T2	709		T3	2		T4	600
valid_sources[0x13]	309981	1			T2	950		T3	6		T4	580
valid_sources[0x14]	270195	1			T2	574		T3	4		T4	632
valid_sources[0x15]	291017	1			T2	895		T3	4		T4	600
valid_sources[0x16]	326165	1			T2	835		T3	2		T4	590
valid_sources[0x17]	356579	1			T2	1064		T3	5		T4	618
valid_sources[0x18]	279680	1			T2	1006		T3	3		T4	629
valid_sources[0x19]	390405	1			T2	905		T3	2		T4	639
valid_sources[0x1a]	320646	1			T2	763		T4	608		T9	25
valid_sources[0x1b]	308129	1			T2	734		T4	605		T9	33
valid_sources[0x1c]	246854	1			T2	846		T3	2		T4	600
valid_sources[0x1d]	282195	1			T2	863		T3	5		T4	617
valid_sources[0x1e]	256824	1			T2	1002		T3	2		T4	586
valid_sources[0x1f]	317605	1			T2	1092		T3	4		T4	586
valid_sources[0x20]	284566	1			T2	783		T3	6		T4	619
valid_sources[0x21]	288175	1			T2	874		T3	7		T4	536
valid_sources[0x22]	258051	1			T2	955		T3	5		T4	672
valid_sources[0x23]	262868	1			T2	831		T3	4		T4	643
valid_sources[0x24]	262056	1			T2	833		T3	2		T4	689
valid_sources[0x25]	321287	1			T2	831		T3	4		T4	590
valid_sources[0x26]	271059	1			T2	929		T3	7		T4	571
valid_sources[0x27]	291547	1			T2	851		T3	2		T4	621
valid_sources[0x28]	330016	1			T2	870		T3	2		T4	593
valid_sources[0x29]	286912	1			T2	1101		T3	6		T4	591
valid_sources[0x2a]	274136	1			T2	959		T3	5		T4	614
valid_sources[0x2b]	288682	1			T2	1013		T3	2		T4	631
valid_sources[0x2c]	340288	1			T2	950		T3	2		T4	599
valid_sources[0x2d]	337044	1			T2	701		T3	2		T4	633
valid_sources[0x2e]	331077	1			T2	963		T3	7		T4	588
valid_sources[0x2f]	245401	1			T2	885		T3	5		T4	599
valid_sources[0x30]	293594	1			T2	925		T3	3		T4	582
valid_sources[0x31]	271698	1			T2	1019		T3	8		T4	660
valid_sources[0x32]	275791	1			T2	948		T3	2		T4	650
valid_sources[0x33]	261840	1			T2	972		T3	6		T4	654
valid_sources[0x34]	335028	1			T2	910		T3	5		T4	624
valid_sources[0x35]	259634	1			T2	1014		T3	3		T4	547
valid_sources[0x36]	277705	1			T2	820		T3	6		T4	591
valid_sources[0x37]	254150	1			T2	844		T3	6		T4	631
valid_sources[0x38]	257472	1			T2	877		T3	6		T4	594
valid_sources[0x39]	293009	1			T2	816		T3	1		T4	642
valid_sources[0x3a]	278614	1			T2	877		T3	7		T4	625
valid_sources[0x3b]	308697	1			T2	1074		T3	6		T4	656
valid_sources[0x3c]	316482	1			T2	868		T3	3		T4	562
valid_sources[0x3d]	242963	1			T2	1005		T3	3		T4	590
valid_sources[0x3e]	325784	1			T2	887		T3	5		T4	661
valid_sources[0x3f]	276427	1			T2	802		T3	2		T4	594
valid_sources[0x40]	277689	1			T2	826		T3	7		T4	631
valid_sources[0x41]	306148	1			T2	881		T3	3		T4	667
valid_sources[0x42]	254933	1			T2	824		T3	5		T4	613
valid_sources[0x43]	258968	1			T2	918		T3	9		T4	665
valid_sources[0x44]	260078	1			T2	685		T3	2		T4	598
valid_sources[0x45]	239811	1			T2	984		T3	2		T4	567
valid_sources[0x46]	302579	1			T2	1008		T3	2		T4	598
valid_sources[0x47]	279638	1			T2	1035		T3	5		T4	596
valid_sources[0x48]	308849	1			T2	830		T3	4		T4	618
valid_sources[0x49]	333822	1			T2	774		T3	6		T4	700
valid_sources[0x4a]	264064	1			T2	711		T3	4		T4	588
valid_sources[0x4b]	371665	1			T2	889		T3	2		T4	589
valid_sources[0x4c]	261567	1			T2	1193		T3	4		T4	618
valid_sources[0x4d]	288476	1			T2	996		T3	3		T4	591
valid_sources[0x4e]	396418	1			T1	14796		T2	960		T3	4
valid_sources[0x4f]	306219	1			T2	828		T3	3		T4	618
valid_sources[0x50]	257814	1			T2	790		T3	5		T4	649
valid_sources[0x51]	256913	1			T2	967		T3	5		T4	620
valid_sources[0x52]	289151	1			T2	795		T3	4		T4	668
valid_sources[0x53]	298857	1			T2	777		T3	6		T4	610
valid_sources[0x54]	274116	1			T1	18253		T2	1052		T3	2
valid_sources[0x55]	369078	1			T2	783		T3	4		T4	654
valid_sources[0x56]	298292	1			T2	832		T3	4		T4	636
valid_sources[0x57]	299351	1			T2	844		T3	3		T4	652
valid_sources[0x58]	251854	1			T2	1118		T3	3		T4	698
valid_sources[0x59]	282461	1			T2	839		T3	4		T4	645
valid_sources[0x5a]	278620	1			T1	2655		T2	767		T3	7
valid_sources[0x5b]	259547	1			T2	946		T3	1		T4	623
valid_sources[0x5c]	313614	1			T2	956		T3	2		T4	661
valid_sources[0x5d]	283380	1			T2	945		T3	3		T4	663
valid_sources[0x5e]	412911	1			T2	999		T3	6		T4	607
valid_sources[0x5f]	324386	1			T2	692		T3	2		T4	621
valid_sources[0x60]	260003	1			T2	705		T3	1		T4	605
valid_sources[0x61]	263671	1			T2	822		T3	5		T4	686
valid_sources[0x62]	263157	1			T2	853		T3	3		T4	629
valid_sources[0x63]	323495	1			T2	893		T3	4		T4	626
valid_sources[0x64]	352939	1			T2	842		T3	2		T4	621
valid_sources[0x65]	282670	1			T2	832		T3	1		T4	639
valid_sources[0x66]	264594	1			T2	953		T3	6		T4	623
valid_sources[0x67]	263144	1			T2	854		T3	4		T4	566
valid_sources[0x68]	289766	1			T2	798		T3	6		T4	681
valid_sources[0x69]	266423	1			T2	965		T3	5		T4	593
valid_sources[0x6a]	251648	1			T2	743		T3	1		T4	596
valid_sources[0x6b]	331427	1			T2	692		T3	6		T4	565
valid_sources[0x6c]	250180	1			T2	805		T3	5		T4	629
valid_sources[0x6d]	399925	1			T2	774		T3	1		T4	650
valid_sources[0x6e]	252606	1			T2	814		T3	3		T4	628
valid_sources[0x6f]	326550	1			T2	789		T3	4		T4	562
valid_sources[0x70]	238727	1			T2	1137		T3	1		T4	545
valid_sources[0x71]	259746	1			T2	764		T3	3		T4	687
valid_sources[0x72]	264201	1			T2	886		T3	3		T4	601
valid_sources[0x73]	248501	1			T2	767		T3	3		T4	584
valid_sources[0x74]	287553	1			T2	994		T3	6		T4	651
valid_sources[0x75]	287706	1			T2	965		T3	8		T4	606
valid_sources[0x76]	242660	1			T2	942		T3	4		T4	595
valid_sources[0x77]	296384	1			T2	851		T3	7		T4	640
valid_sources[0x78]	331739	1			T2	1028		T3	6		T4	612
valid_sources[0x79]	241768	1			T2	678		T3	7		T4	661
valid_sources[0x7a]	268883	1			T2	1037		T3	3		T4	635
valid_sources[0x7b]	257045	1			T2	873		T3	7		T4	600
valid_sources[0x7c]	258391	1			T2	882		T3	6		T4	578
valid_sources[0x7d]	304628	1			T2	1086		T3	6		T4	538
valid_sources[0x7e]	293006	1			T2	1009		T3	3		T4	568
valid_sources[0x7f]	294252	1			T2	844		T3	1		T4	642
valid_sources[0x80]	313557	1			T2	828		T3	6		T4	596

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29624607

1

T1

18711

T2

103798

T3

4

values[0x0]

all_enables

biggest_size

14905225

1

T1

9260

T2

52071

T3

40

values[0x1]

all_enables

biggest_size

14910885

1

T1

9393

T2

51724

T3

30

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37257	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129901

1

T1

7

T2

5

T4

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48892	1			T1	5		T4	15		T10	416
values[0x0]	57038	1			T1	9		T2	3		T4	33
values[0x1]	61228	1			T1	9		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138791

1

T1

7

T2

5

T4

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	563	1			T25	9		T51	13		T144	1
valid_sources[0x01]	851	1			T10	20		T25	7		T21	1
valid_sources[0x02]	527	1			T10	1		T5	1		T42	2
valid_sources[0x03]	520	1			T10	3		T24	4		T25	19
valid_sources[0x04]	542	1			T4	1		T10	1		T148	1
valid_sources[0x05]	775	1			T24	2		T25	22		T51	4
valid_sources[0x06]	871	1			T10	2		T20	1		T25	6
valid_sources[0x07]	500	1			T10	2		T148	1		T20	1
valid_sources[0x08]	415	1			T10	4		T24	2		T25	1
valid_sources[0x09]	612	1			T10	4		T13	1		T24	2
valid_sources[0x0a]	754	1			T10	11		T42	12		T20	2
valid_sources[0x0b]	662	1			T4	1		T10	6		T19	3
valid_sources[0x0c]	608	1			T10	8		T24	8		T25	14
valid_sources[0x0d]	637	1			T10	1		T24	7		T25	16
valid_sources[0x0e]	433	1			T4	1		T6	1		T26	2
valid_sources[0x0f]	780	1			T4	1		T10	1		T26	4
valid_sources[0x10]	542	1			T10	21		T25	5		T51	5
valid_sources[0x11]	585	1			T10	15		T20	1		T24	3
valid_sources[0x12]	919	1			T10	42		T26	2		T42	7
valid_sources[0x13]	498	1			T4	1		T10	7		T6	2
valid_sources[0x14]	1167	1			T42	3		T20	1		T25	10
valid_sources[0x15]	488	1			T10	1		T24	10		T25	5
valid_sources[0x16]	801	1			T4	1		T10	10		T6	2
valid_sources[0x17]	644	1			T1	5		T10	10		T20	1
valid_sources[0x18]	443	1			T10	7		T42	2		T20	1
valid_sources[0x19]	910	1			T10	2		T19	2		T148	1
valid_sources[0x1a]	519	1			T4	2		T25	20		T140	1
valid_sources[0x1b]	689	1			T10	16		T51	10		T144	1
valid_sources[0x1c]	683	1			T4	1		T10	4		T6	2
valid_sources[0x1d]	887	1			T20	1		T25	8		T51	6
valid_sources[0x1e]	745	1			T1	1		T4	1		T10	1
valid_sources[0x1f]	762	1			T4	2		T10	11		T20	1
valid_sources[0x20]	917	1			T10	22		T26	1		T24	10
valid_sources[0x21]	624	1			T10	2		T20	1		T25	3
valid_sources[0x22]	636	1			T2	1		T4	2		T10	5
valid_sources[0x23]	939	1			T10	10		T24	3		T25	12
valid_sources[0x24]	505	1			T10	12		T51	13		T69	6
valid_sources[0x25]	638	1			T10	2		T43	4		T24	4
valid_sources[0x26]	937	1			T4	2		T10	4		T46	1
valid_sources[0x27]	619	1			T6	2		T19	2		T20	1
valid_sources[0x28]	505	1			T10	20		T21	10		T140	1
valid_sources[0x29]	769	1			T10	20		T149	2		T24	5
valid_sources[0x2a]	662	1			T10	22		T42	1		T20	2
valid_sources[0x2b]	589	1			T10	5		T25	4		T15	1
valid_sources[0x2c]	490	1			T4	1		T6	3		T24	6
valid_sources[0x2d]	472	1			T10	24		T24	2		T25	5
valid_sources[0x2e]	713	1			T10	23		T42	3		T19	2
valid_sources[0x2f]	637	1			T10	9		T26	2		T24	11
valid_sources[0x30]	867	1			T10	8		T6	5		T25	13
valid_sources[0x31]	562	1			T10	1		T24	1		T25	7
valid_sources[0x32]	1270	1			T10	8		T24	6		T25	4
valid_sources[0x33]	815	1			T4	2		T10	2		T19	1
valid_sources[0x34]	511	1			T4	1		T24	8		T25	14
valid_sources[0x35]	770	1			T1	3		T4	1		T26	2
valid_sources[0x36]	589	1			T20	1		T24	3		T25	15
valid_sources[0x37]	644	1			T10	2		T6	6		T20	1
valid_sources[0x38]	490	1			T4	1		T10	1		T13	1
valid_sources[0x39]	599	1			T148	1		T20	3		T24	8
valid_sources[0x3a]	531	1			T4	1		T20	1		T25	18
valid_sources[0x3b]	509	1			T20	1		T24	1		T25	15
valid_sources[0x3c]	694	1			T3	1		T6	1		T24	1
valid_sources[0x3d]	541	1			T10	11		T13	1		T24	26
valid_sources[0x3e]	538	1			T25	23		T51	11		T22	3
valid_sources[0x3f]	614	1			T10	2		T24	1		T25	10
valid_sources[0x40]	631	1			T10	4		T24	9		T123	18
valid_sources[0x41]	560	1			T10	8		T24	6		T25	23
valid_sources[0x42]	599	1			T10	3		T24	3		T150	2
valid_sources[0x43]	744	1			T20	1		T24	7		T25	12
valid_sources[0x44]	922	1			T151	1		T24	8		T25	20
valid_sources[0x45]	536	1			T4	1		T46	1		T20	1
valid_sources[0x46]	791	1			T10	11		T41	1		T19	1
valid_sources[0x47]	479	1			T1	2		T20	1		T47	3
valid_sources[0x48]	695	1			T10	12		T24	3		T25	2
valid_sources[0x49]	518	1			T24	3		T25	22		T51	3
valid_sources[0x4a]	639	1			T10	1		T43	1		T152	1
valid_sources[0x4b]	791	1			T10	1		T98	1		T152	1
valid_sources[0x4c]	860	1			T10	2		T24	5		T25	9
valid_sources[0x4d]	593	1			T10	12		T20	1		T24	5
valid_sources[0x4e]	818	1			T10	3		T57	2		T20	1
valid_sources[0x4f]	457	1			T4	1		T10	2		T6	1
valid_sources[0x50]	568	1			T10	8		T24	4		T25	10
valid_sources[0x51]	457	1			T6	1		T26	1		T148	1
valid_sources[0x52]	640	1			T10	3		T64	3		T24	1
valid_sources[0x53]	642	1			T10	1		T24	2		T25	6
valid_sources[0x54]	585	1			T10	13		T148	1		T20	2
valid_sources[0x55]	599	1			T10	11		T19	1		T24	10
valid_sources[0x56]	619	1			T10	12		T153	1		T24	1
valid_sources[0x57]	774	1			T4	1		T24	3		T25	5
valid_sources[0x58]	484	1			T10	11		T26	3		T20	1
valid_sources[0x59]	663	1			T10	4		T20	2		T24	10
valid_sources[0x5a]	509	1			T19	10		T20	2		T24	1
valid_sources[0x5b]	527	1			T4	1		T10	7		T24	2
valid_sources[0x5c]	545	1			T4	1		T20	1		T24	1
valid_sources[0x5d]	575	1			T10	3		T148	1		T20	1
valid_sources[0x5e]	458	1			T10	31		T43	1		T25	3
valid_sources[0x5f]	536	1			T10	13		T24	12		T25	8
valid_sources[0x60]	639	1			T10	7		T26	3		T153	1
valid_sources[0x61]	483	1			T10	3		T24	1		T25	2
valid_sources[0x62]	803	1			T4	1		T43	7		T24	16
valid_sources[0x63]	589	1			T20	2		T24	2		T25	7
valid_sources[0x64]	792	1			T10	14		T11	1		T98	1
valid_sources[0x65]	671	1			T10	3		T20	1		T24	27
valid_sources[0x66]	780	1			T4	1		T10	2		T19	2
valid_sources[0x67]	606	1			T4	2		T10	14		T19	10
valid_sources[0x68]	652	1			T10	11		T11	1		T20	1
valid_sources[0x69]	642	1			T1	2		T10	11		T26	4
valid_sources[0x6a]	835	1			T10	8		T24	6		T140	6
valid_sources[0x6b]	1072	1			T4	1		T10	5		T24	1
valid_sources[0x6c]	1127	1			T10	7		T20	1		T24	8
valid_sources[0x6d]	499	1			T10	12		T46	1		T24	12
valid_sources[0x6e]	562	1			T10	8		T24	3		T25	6
valid_sources[0x6f]	598	1			T4	1		T10	2		T5	2
valid_sources[0x70]	844	1			T4	1		T10	13		T46	1
valid_sources[0x71]	728	1			T4	1		T10	14		T41	2
valid_sources[0x72]	761	1			T10	16		T41	1		T19	2
valid_sources[0x73]	1003	1			T24	3		T25	3		T140	8
valid_sources[0x74]	564	1			T10	1		T24	7		T25	4
valid_sources[0x75]	496	1			T6	1		T25	5		T54	4
valid_sources[0x76]	666	1			T6	3		T46	1		T24	7
valid_sources[0x77]	445	1			T10	2		T24	1		T25	9
valid_sources[0x78]	497	1			T4	1		T10	18		T24	2
valid_sources[0x79]	428	1			T10	1		T20	1		T24	2
valid_sources[0x7a]	683	1			T4	1		T20	1		T152	1
valid_sources[0x7b]	565	1			T10	1		T99	3		T65	14
valid_sources[0x7c]	525	1			T10	1		T19	1		T20	1
valid_sources[0x7d]	812	1			T10	15		T25	21		T154	1
valid_sources[0x7e]	636	1			T10	4		T20	1		T24	6
valid_sources[0x7f]	889	1			T4	4		T10	2		T26	1
valid_sources[0x80]	580	1			T4	1		T19	2		T43	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35785

1

T1

2

T4

3

T10

378

values[0x0]

all_enables

biggest_size

48165

1

T1

3

T2

3

T4

13

values[0x1]

all_enables

biggest_size

45951

1

T1

2

T2

2

T4

3