Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13822736

1

T1

3185

T2

20536

T3

934

full_word

54164091

1

T1

29936

T2

207593

T3

74

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67986537	1			T1	33121		T2	228129		T3	1008
auto[TlIntgErrCmd]	90	1			T61	2		T62	7		T63	6
auto[TlIntgErrData]	105	1			T61	2		T62	9		T63	11
auto[TlIntgErrBoth]	95	1			T61	6		T62	4		T63	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31018089

1

T1

12449

T2

114011

T3

372

auto[1]

36968738

1

T1

20672

T2

114118

T3

636

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6599136	1			T1	1166		T2	10213		T3	368
auto[TlIntgErrNone]	partial	auto[1]	7223335	1			T1	2019		T2	10323		T3	566
auto[TlIntgErrNone]	full_word	auto[0]	24418829	1			T1	11283		T2	103798		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	29745237	1			T1	18653		T2	103795		T3	70
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T61	1		T62	4		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T61	1		T62	2		T63	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T129	1		T136	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T62	1		T130	1		T134	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T61	1		T62	3		T63	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T62	6		T63	9		T129	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T129	1		T132	2		T137	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T61	1		T129	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T61	3		T62	2		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T61	3		T62	2		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T138	1		T139	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T63	1		T129	1		T131	1