Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	835542	1			T3	54		T4	682		T5	4862
auto[1]	9884577	1			T1	1190		T2	95084		T3	50
auto[2]	704305	1			T3	52		T4	441		T5	3600
auto[3]	9756393	1			T1	1265		T2	95004		T3	141

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13886803	1			T1	2023		T2	158792		T3	1
auto[1]	1983835	1			T1	211		T2	14955		T3	7
auto[2]	2008700	1			T1	206		T2	14993		T3	14
auto[3]	3301479	1			T1	15		T2	1348		T3	275

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8235502

1

T1

2454

T3

297

T4

1844

auto[1]

12945315

1

T1

1

T2

190088

T9

11

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	297684	1			T4	555		T12	6		T45	751
auto[0]	auto[0]	auto[1]	31313	1			T4	61		T12	1		T45	74
auto[0]	auto[0]	auto[2]	31078	1			T4	58		T56	1		T45	78
auto[0]	auto[0]	auto[3]	10117	1			T3	54		T4	8		T56	222
auto[0]	auto[1]	auto[0]	3102377	1			T1	987		T4	370		T9	3257
auto[0]	auto[1]	auto[1]	317376	1			T1	94		T4	71		T5	1
auto[0]	auto[1]	auto[2]	310251	1			T1	101		T3	2		T4	36
auto[0]	auto[1]	auto[3]	65638	1			T1	7		T3	48		T4	8
auto[0]	auto[2]	auto[0]	257183	1			T4	344		T45	660		T21	1
auto[0]	auto[2]	auto[1]	26986	1			T3	2		T4	31		T56	19
auto[0]	auto[2]	auto[2]	28432	1			T4	61		T12	6		T45	63
auto[0]	auto[2]	auto[3]	8396	1			T3	50		T4	5		T5	2
auto[0]	auto[3]	auto[0]	3061263	1			T1	1035		T3	1		T4	146
auto[0]	auto[3]	auto[1]	304436	1			T1	117		T3	5		T4	19
auto[0]	auto[3]	auto[2]	316191	1			T1	105		T3	12		T4	64
auto[0]	auto[3]	auto[3]	66781	1			T1	8		T3	123		T4	7
auto[1]	auto[0]	auto[0]	15765	1			T5	184		T41	508		T99	312
auto[1]	auto[0]	auto[1]	69330	1			T5	705		T41	2267		T99	1403
auto[1]	auto[0]	auto[2]	68635	1			T5	771		T41	2201		T99	1353
auto[1]	auto[0]	auto[3]	311620	1			T5	3202		T41	9991		T99	6137
auto[1]	auto[1]	auto[0]	3574296	1			T1	1		T2	79526		T9	5
auto[1]	auto[1]	auto[1]	619999	1			T2	7007		T5	2238		T11	5625
auto[1]	auto[1]	auto[2]	583860	1			T2	7890		T5	1340		T11	5755
auto[1]	auto[1]	auto[3]	1310780	1			T2	661		T5	10048		T11	617
auto[1]	auto[2]	auto[0]	11516	1			T41	433		T45	2		T99	165
auto[1]	auto[2]	auto[1]	50177	1			T41	2080		T99	860		T100	839
auto[1]	auto[2]	auto[2]	58748	1			T5	680		T41	1562		T99	1288
auto[1]	auto[2]	auto[3]	262867	1			T5	2918		T41	6945		T99	5827
auto[1]	auto[3]	auto[0]	3566719	1			T2	79266		T9	6		T5	140
auto[1]	auto[3]	auto[1]	564218	1			T2	7948		T5	594		T11	5778
auto[1]	auto[3]	auto[2]	611505	1			T2	7103		T5	2168		T11	5774
auto[1]	auto[3]	auto[3]	1265280	1			T2	687		T5	9502		T11	524