Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	323753108	192087	0	0
ctrl_regwen_rd_A	323753108	4294	0	0
exec_rd_A	323753108	3824	0	0
exec_regwen_rd_A	323753108	4242	0	0
readback_rd_A	323753108	2610	0	0
readback_regwen_rd_A	323753108	2470	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323753108	192087	0	0
T5	154633	0	0	0
T6	49512	0	0	0
T10	17180	1913	0	0
T11	201744	0	0	0
T12	103432	0	0	0
T24	0	2102	0	0
T25	0	3635	0	0
T26	444754	0	0	0
T41	102913	0	0	0
T42	458949	0	0	0
T48	0	5336	0	0
T51	0	3074	0	0
T56	16492	0	0	0
T57	4338	0	0	0
T59	0	3197	0	0
T60	0	1287	0	0
T69	0	1784	0	0
T70	0	1301	0	0
T71	0	1628	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323753108	4294	0	0
T7	39416	0	0	0
T8	827873	0	0	0
T14	1133	0	0	0
T21	46837	0	0	0
T24	62541	173	0	0
T25	100857	0	0	0
T48	0	412	0	0
T49	0	338	0	0
T59	0	264	0	0
T116	0	186	0	0
T117	0	159	0	0
T118	0	549	0	0
T119	0	18	0	0
T120	0	149	0	0
T121	0	348	0	0
T122	9388	0	0	0
T123	389170	0	0	0
T124	542283	0	0	0
T125	43603	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323753108	3824	0	0
T7	39416	0	0	0
T8	827873	0	0	0
T14	1133	0	0	0
T21	46837	0	0	0
T24	62541	169	0	0
T25	100857	0	0	0
T48	0	325	0	0
T49	0	373	0	0
T59	0	274	0	0
T116	0	103	0	0
T117	0	129	0	0
T118	0	389	0	0
T119	0	46	0	0
T120	0	134	0	0
T121	0	262	0	0
T122	9388	0	0	0
T123	389170	0	0	0
T124	542283	0	0	0
T125	43603	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323753108	4242	0	0
T7	39416	0	0	0
T8	827873	0	0	0
T14	1133	0	0	0
T21	46837	0	0	0
T24	62541	131	0	0
T25	100857	0	0	0
T48	0	374	0	0
T49	0	403	0	0
T59	0	310	0	0
T116	0	105	0	0
T117	0	170	0	0
T118	0	485	0	0
T119	0	72	0	0
T120	0	161	0	0
T121	0	286	0	0
T122	9388	0	0	0
T123	389170	0	0	0
T124	542283	0	0	0
T125	43603	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323753108	2610	0	0
T7	39416	0	0	0
T8	827873	0	0	0
T14	1133	0	0	0
T21	46837	0	0	0
T24	62541	94	0	0
T25	100857	0	0	0
T48	0	341	0	0
T49	0	309	0	0
T59	0	305	0	0
T116	0	100	0	0
T117	0	145	0	0
T118	0	431	0	0
T119	0	81	0	0
T120	0	101	0	0
T121	0	237	0	0
T122	9388	0	0	0
T123	389170	0	0	0
T124	542283	0	0	0
T125	43603	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323753108	2470	0	0
T7	39416	0	0	0
T8	827873	0	0	0
T14	1133	0	0	0
T21	46837	0	0	0
T24	62541	89	0	0
T25	100857	0	0	0
T48	0	306	0	0
T49	0	319	0	0
T59	0	264	0	0
T116	0	115	0	0
T117	0	104	0	0
T118	0	445	0	0
T119	0	54	0	0
T120	0	105	0	0
T121	0	230	0	0
T122	9388	0	0	0
T123	389170	0	0	0
T124	542283	0	0	0
T125	43603	0	0	0