| T794 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4116303928 |
|
|
Aug 03 05:59:45 PM PDT 24 |
Aug 03 06:02:36 PM PDT 24 |
622121708 ps |
| T795 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3107055737 |
|
|
Aug 03 05:56:12 PM PDT 24 |
Aug 03 06:01:52 PM PDT 24 |
17009554832 ps |
| T796 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.4248182277 |
|
|
Aug 03 05:55:37 PM PDT 24 |
Aug 03 06:03:45 PM PDT 24 |
8018419318 ps |
| T797 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.96269842 |
|
|
Aug 03 06:03:35 PM PDT 24 |
Aug 03 06:14:07 PM PDT 24 |
2006269363 ps |
| T87 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1855345273 |
|
|
Aug 03 05:54:21 PM PDT 24 |
Aug 03 05:54:26 PM PDT 24 |
95336116 ps |
| T798 |
/workspace/coverage/default/23.sram_ctrl_regwen.607032330 |
|
|
Aug 03 05:57:45 PM PDT 24 |
Aug 03 05:58:57 PM PDT 24 |
2654947138 ps |
| T799 |
/workspace/coverage/default/20.sram_ctrl_bijection.1609191957 |
|
|
Aug 03 05:56:27 PM PDT 24 |
Aug 03 05:57:16 PM PDT 24 |
4368200460 ps |
| T800 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2267213533 |
|
|
Aug 03 06:01:42 PM PDT 24 |
Aug 03 06:04:07 PM PDT 24 |
134338631 ps |
| T801 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.437104626 |
|
|
Aug 03 06:03:57 PM PDT 24 |
Aug 03 06:11:03 PM PDT 24 |
4522690305 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_smoke.4136227818 |
|
|
Aug 03 05:54:10 PM PDT 24 |
Aug 03 05:54:20 PM PDT 24 |
605797663 ps |
| T803 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3873783080 |
|
|
Aug 03 05:53:35 PM PDT 24 |
Aug 03 05:56:54 PM PDT 24 |
2095247905 ps |
| T804 |
/workspace/coverage/default/36.sram_ctrl_regwen.2510125272 |
|
|
Aug 03 06:02:09 PM PDT 24 |
Aug 03 06:15:38 PM PDT 24 |
33103585639 ps |
| T805 |
/workspace/coverage/default/10.sram_ctrl_smoke.2747424767 |
|
|
Aug 03 05:54:05 PM PDT 24 |
Aug 03 05:54:56 PM PDT 24 |
105169097 ps |
| T806 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.649978896 |
|
|
Aug 03 06:05:07 PM PDT 24 |
Aug 03 06:09:01 PM PDT 24 |
5575297552 ps |
| T807 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3710746630 |
|
|
Aug 03 06:01:31 PM PDT 24 |
Aug 03 06:01:32 PM PDT 24 |
52149164 ps |
| T808 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2438179409 |
|
|
Aug 03 05:57:41 PM PDT 24 |
Aug 03 05:58:26 PM PDT 24 |
194149774 ps |
| T809 |
/workspace/coverage/default/19.sram_ctrl_stress_all.69411418 |
|
|
Aug 03 05:56:22 PM PDT 24 |
Aug 03 07:07:51 PM PDT 24 |
60747694802 ps |
| T810 |
/workspace/coverage/default/24.sram_ctrl_executable.3285272645 |
|
|
Aug 03 05:58:08 PM PDT 24 |
Aug 03 06:20:49 PM PDT 24 |
77042187447 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2917765683 |
|
|
Aug 03 06:00:58 PM PDT 24 |
Aug 03 06:01:03 PM PDT 24 |
883895358 ps |
| T812 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.4064553585 |
|
|
Aug 03 05:55:45 PM PDT 24 |
Aug 03 05:55:48 PM PDT 24 |
243414816 ps |
| T813 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.634390250 |
|
|
Aug 03 05:58:21 PM PDT 24 |
Aug 03 06:02:18 PM PDT 24 |
37948476077 ps |
| T814 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.4033244147 |
|
|
Aug 03 05:58:06 PM PDT 24 |
Aug 03 05:58:07 PM PDT 24 |
31306295 ps |
| T815 |
/workspace/coverage/default/18.sram_ctrl_regwen.1486718760 |
|
|
Aug 03 05:56:03 PM PDT 24 |
Aug 03 06:09:13 PM PDT 24 |
84097852887 ps |
| T816 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1015729681 |
|
|
Aug 03 06:00:46 PM PDT 24 |
Aug 03 06:58:42 PM PDT 24 |
219276508475 ps |
| T817 |
/workspace/coverage/default/35.sram_ctrl_executable.4261639765 |
|
|
Aug 03 06:01:48 PM PDT 24 |
Aug 03 06:07:17 PM PDT 24 |
17240121593 ps |
| T818 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.4250402806 |
|
|
Aug 03 06:04:34 PM PDT 24 |
Aug 03 06:04:45 PM PDT 24 |
663255512 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2375592224 |
|
|
Aug 03 06:04:29 PM PDT 24 |
Aug 03 06:24:49 PM PDT 24 |
16645481982 ps |
| T820 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3468647609 |
|
|
Aug 03 05:59:56 PM PDT 24 |
Aug 03 05:59:57 PM PDT 24 |
19932569 ps |
| T821 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4179396951 |
|
|
Aug 03 06:04:48 PM PDT 24 |
Aug 03 06:11:27 PM PDT 24 |
15277142751 ps |
| T822 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3978444559 |
|
|
Aug 03 05:53:27 PM PDT 24 |
Aug 03 05:57:22 PM PDT 24 |
11760176474 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1801748826 |
|
|
Aug 03 06:02:51 PM PDT 24 |
Aug 03 06:02:57 PM PDT 24 |
2743322907 ps |
| T824 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4097494775 |
|
|
Aug 03 05:53:28 PM PDT 24 |
Aug 03 05:58:38 PM PDT 24 |
12537778406 ps |
| T825 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2786133901 |
|
|
Aug 03 05:53:26 PM PDT 24 |
Aug 03 06:57:54 PM PDT 24 |
190576112961 ps |
| T826 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2603841067 |
|
|
Aug 03 05:58:27 PM PDT 24 |
Aug 03 05:58:28 PM PDT 24 |
48361772 ps |
| T827 |
/workspace/coverage/default/21.sram_ctrl_bijection.1241427207 |
|
|
Aug 03 05:56:45 PM PDT 24 |
Aug 03 05:57:49 PM PDT 24 |
7510412282 ps |
| T828 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1232732066 |
|
|
Aug 03 05:57:25 PM PDT 24 |
Aug 03 05:57:30 PM PDT 24 |
473459158 ps |
| T829 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.4267545541 |
|
|
Aug 03 06:02:11 PM PDT 24 |
Aug 03 06:02:16 PM PDT 24 |
2699454475 ps |
| T830 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2238270775 |
|
|
Aug 03 05:53:08 PM PDT 24 |
Aug 03 05:56:42 PM PDT 24 |
16106965308 ps |
| T831 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1988376757 |
|
|
Aug 03 06:03:42 PM PDT 24 |
Aug 03 06:07:56 PM PDT 24 |
2701246548 ps |
| T832 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2385223959 |
|
|
Aug 03 06:04:34 PM PDT 24 |
Aug 03 06:06:55 PM PDT 24 |
141359838 ps |
| T833 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1809230051 |
|
|
Aug 03 06:03:16 PM PDT 24 |
Aug 03 06:03:54 PM PDT 24 |
1625747794 ps |
| T834 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3557751782 |
|
|
Aug 03 06:04:41 PM PDT 24 |
Aug 03 06:04:42 PM PDT 24 |
36289929 ps |
| T835 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3847206146 |
|
|
Aug 03 05:53:21 PM PDT 24 |
Aug 03 06:02:25 PM PDT 24 |
21654649758 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3100595672 |
|
|
Aug 03 06:00:02 PM PDT 24 |
Aug 03 06:00:07 PM PDT 24 |
1553843944 ps |
| T837 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2397562972 |
|
|
Aug 03 06:04:12 PM PDT 24 |
Aug 03 06:04:13 PM PDT 24 |
17542240 ps |
| T838 |
/workspace/coverage/default/47.sram_ctrl_bijection.1362190888 |
|
|
Aug 03 06:05:04 PM PDT 24 |
Aug 03 06:05:45 PM PDT 24 |
2374645013 ps |
| T839 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.788682737 |
|
|
Aug 03 05:55:24 PM PDT 24 |
Aug 03 06:09:45 PM PDT 24 |
2666408981 ps |
| T840 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3558402513 |
|
|
Aug 03 06:03:16 PM PDT 24 |
Aug 03 06:25:10 PM PDT 24 |
4399240507 ps |
| T841 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3430032047 |
|
|
Aug 03 05:53:29 PM PDT 24 |
Aug 03 05:59:23 PM PDT 24 |
3556931969 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3064821179 |
|
|
Aug 03 05:57:01 PM PDT 24 |
Aug 03 05:57:40 PM PDT 24 |
94974342 ps |
| T843 |
/workspace/coverage/default/30.sram_ctrl_regwen.3897386249 |
|
|
Aug 03 06:00:07 PM PDT 24 |
Aug 03 06:03:47 PM PDT 24 |
13055732063 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_bijection.2211930194 |
|
|
Aug 03 06:03:42 PM PDT 24 |
Aug 03 06:05:05 PM PDT 24 |
27849578726 ps |
| T845 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2087252712 |
|
|
Aug 03 05:54:37 PM PDT 24 |
Aug 03 06:27:26 PM PDT 24 |
9794256729 ps |
| T846 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3756424729 |
|
|
Aug 03 05:54:52 PM PDT 24 |
Aug 03 05:55:01 PM PDT 24 |
149100743 ps |
| T847 |
/workspace/coverage/default/4.sram_ctrl_partial_access.4152538983 |
|
|
Aug 03 05:53:25 PM PDT 24 |
Aug 03 05:53:33 PM PDT 24 |
2052348200 ps |
| T848 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1649871242 |
|
|
Aug 03 06:02:23 PM PDT 24 |
Aug 03 06:04:41 PM PDT 24 |
7521637573 ps |
| T849 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1539129752 |
|
|
Aug 03 06:03:56 PM PDT 24 |
Aug 03 06:15:36 PM PDT 24 |
1173395358 ps |
| T850 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1662690714 |
|
|
Aug 03 05:53:38 PM PDT 24 |
Aug 03 05:59:23 PM PDT 24 |
3670553576 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_regwen.564680141 |
|
|
Aug 03 05:57:02 PM PDT 24 |
Aug 03 06:30:03 PM PDT 24 |
12907601468 ps |
| T852 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.920668874 |
|
|
Aug 03 06:03:09 PM PDT 24 |
Aug 03 06:03:24 PM PDT 24 |
426961411 ps |
| T853 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2768731384 |
|
|
Aug 03 06:04:07 PM PDT 24 |
Aug 03 06:04:12 PM PDT 24 |
236535808 ps |
| T854 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3660206151 |
|
|
Aug 03 05:54:09 PM PDT 24 |
Aug 03 05:54:15 PM PDT 24 |
97992542 ps |
| T855 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.441435577 |
|
|
Aug 03 05:53:07 PM PDT 24 |
Aug 03 05:53:08 PM PDT 24 |
151100044 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4268148370 |
|
|
Aug 03 05:57:30 PM PDT 24 |
Aug 03 06:01:35 PM PDT 24 |
7996821198 ps |
| T857 |
/workspace/coverage/default/26.sram_ctrl_bijection.2046145353 |
|
|
Aug 03 05:58:42 PM PDT 24 |
Aug 03 05:59:09 PM PDT 24 |
1668073310 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3388779725 |
|
|
Aug 03 05:59:19 PM PDT 24 |
Aug 03 06:06:43 PM PDT 24 |
72735443378 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_smoke.1011832553 |
|
|
Aug 03 06:03:42 PM PDT 24 |
Aug 03 06:03:54 PM PDT 24 |
2832946522 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.4065296383 |
|
|
Aug 03 06:03:04 PM PDT 24 |
Aug 03 06:03:05 PM PDT 24 |
201229366 ps |
| T861 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.455642621 |
|
|
Aug 03 05:56:46 PM PDT 24 |
Aug 03 06:11:27 PM PDT 24 |
10764603690 ps |
| T862 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1366389032 |
|
|
Aug 03 05:57:51 PM PDT 24 |
Aug 03 07:47:41 PM PDT 24 |
458623916603 ps |
| T863 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3281701977 |
|
|
Aug 03 05:53:57 PM PDT 24 |
Aug 03 05:53:58 PM PDT 24 |
46436889 ps |
| T864 |
/workspace/coverage/default/28.sram_ctrl_executable.3346949842 |
|
|
Aug 03 05:59:33 PM PDT 24 |
Aug 03 06:01:34 PM PDT 24 |
16205203620 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1531519253 |
|
|
Aug 03 05:53:21 PM PDT 24 |
Aug 03 05:53:24 PM PDT 24 |
562196323 ps |
| T865 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3172446019 |
|
|
Aug 03 05:53:21 PM PDT 24 |
Aug 03 06:06:08 PM PDT 24 |
4272556237 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2990052839 |
|
|
Aug 03 05:58:12 PM PDT 24 |
Aug 03 05:58:17 PM PDT 24 |
69937961 ps |
| T867 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3278857853 |
|
|
Aug 03 05:53:32 PM PDT 24 |
Aug 03 05:53:43 PM PDT 24 |
443563779 ps |
| T868 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1847538338 |
|
|
Aug 03 06:04:33 PM PDT 24 |
Aug 03 06:04:34 PM PDT 24 |
45067541 ps |
| T869 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.949732852 |
|
|
Aug 03 05:53:07 PM PDT 24 |
Aug 03 05:54:41 PM PDT 24 |
4956438949 ps |
| T870 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2361442548 |
|
|
Aug 03 05:53:13 PM PDT 24 |
Aug 03 05:53:18 PM PDT 24 |
2897027743 ps |
| T871 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4091662734 |
|
|
Aug 03 05:53:42 PM PDT 24 |
Aug 03 05:53:45 PM PDT 24 |
214578177 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1991994065 |
|
|
Aug 03 05:57:20 PM PDT 24 |
Aug 03 05:58:07 PM PDT 24 |
401559319 ps |
| T873 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.407799370 |
|
|
Aug 03 05:55:02 PM PDT 24 |
Aug 03 05:55:12 PM PDT 24 |
442510592 ps |
| T874 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2598859954 |
|
|
Aug 03 06:05:06 PM PDT 24 |
Aug 03 06:05:06 PM PDT 24 |
29284023 ps |
| T875 |
/workspace/coverage/default/6.sram_ctrl_bijection.3636815202 |
|
|
Aug 03 05:53:32 PM PDT 24 |
Aug 03 05:54:01 PM PDT 24 |
21542317399 ps |
| T876 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2671187216 |
|
|
Aug 03 06:01:40 PM PDT 24 |
Aug 03 06:10:05 PM PDT 24 |
43516186202 ps |
| T877 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2278335913 |
|
|
Aug 03 05:53:27 PM PDT 24 |
Aug 03 05:54:01 PM PDT 24 |
381957069 ps |
| T878 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3657477676 |
|
|
Aug 03 06:05:07 PM PDT 24 |
Aug 03 06:05:10 PM PDT 24 |
86240357 ps |
| T879 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.713931489 |
|
|
Aug 03 06:04:08 PM PDT 24 |
Aug 03 06:18:51 PM PDT 24 |
12260166800 ps |
| T880 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.543477355 |
|
|
Aug 03 05:54:28 PM PDT 24 |
Aug 03 06:03:57 PM PDT 24 |
11541264323 ps |
| T881 |
/workspace/coverage/default/38.sram_ctrl_stress_all.408298026 |
|
|
Aug 03 06:02:54 PM PDT 24 |
Aug 03 06:25:25 PM PDT 24 |
14247508258 ps |
| T882 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1292654757 |
|
|
Aug 03 05:53:23 PM PDT 24 |
Aug 03 05:58:38 PM PDT 24 |
4391992627 ps |
| T883 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.4254505522 |
|
|
Aug 03 05:58:28 PM PDT 24 |
Aug 03 06:26:38 PM PDT 24 |
3608848606 ps |
| T884 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.4256724460 |
|
|
Aug 03 05:57:50 PM PDT 24 |
Aug 03 06:09:58 PM PDT 24 |
1761205489 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3657136089 |
|
|
Aug 03 05:55:36 PM PDT 24 |
Aug 03 05:55:37 PM PDT 24 |
35984348 ps |
| T886 |
/workspace/coverage/default/29.sram_ctrl_smoke.1671100957 |
|
|
Aug 03 05:59:37 PM PDT 24 |
Aug 03 06:01:55 PM PDT 24 |
2282307979 ps |
| T887 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1513750905 |
|
|
Aug 03 05:53:22 PM PDT 24 |
Aug 03 05:53:27 PM PDT 24 |
176325616 ps |
| T888 |
/workspace/coverage/default/38.sram_ctrl_smoke.3701879439 |
|
|
Aug 03 06:02:37 PM PDT 24 |
Aug 03 06:02:51 PM PDT 24 |
3423604762 ps |
| T889 |
/workspace/coverage/default/31.sram_ctrl_regwen.515972326 |
|
|
Aug 03 06:00:27 PM PDT 24 |
Aug 03 06:06:44 PM PDT 24 |
4292755741 ps |
| T890 |
/workspace/coverage/default/4.sram_ctrl_smoke.1168371709 |
|
|
Aug 03 05:53:24 PM PDT 24 |
Aug 03 05:53:26 PM PDT 24 |
95979447 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.849360352 |
|
|
Aug 03 05:57:06 PM PDT 24 |
Aug 03 05:57:10 PM PDT 24 |
344269161 ps |
| T892 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.2100692471 |
|
|
Aug 03 05:59:32 PM PDT 24 |
Aug 03 05:59:38 PM PDT 24 |
1247230524 ps |
| T893 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2948977522 |
|
|
Aug 03 05:53:31 PM PDT 24 |
Aug 03 05:53:36 PM PDT 24 |
378376218 ps |
| T894 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1214895760 |
|
|
Aug 03 06:02:33 PM PDT 24 |
Aug 03 06:02:38 PM PDT 24 |
72310895 ps |
| T895 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1554679269 |
|
|
Aug 03 06:04:47 PM PDT 24 |
Aug 03 06:04:50 PM PDT 24 |
74635990 ps |
| T896 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2142126605 |
|
|
Aug 03 05:54:25 PM PDT 24 |
Aug 03 06:17:49 PM PDT 24 |
4450593762 ps |
| T897 |
/workspace/coverage/default/44.sram_ctrl_partial_access.56755695 |
|
|
Aug 03 06:04:21 PM PDT 24 |
Aug 03 06:04:27 PM PDT 24 |
1116462357 ps |
| T898 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.313439145 |
|
|
Aug 03 05:53:33 PM PDT 24 |
Aug 03 05:53:36 PM PDT 24 |
361717537 ps |
| T899 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.4239686177 |
|
|
Aug 03 05:53:22 PM PDT 24 |
Aug 03 05:53:26 PM PDT 24 |
1375189345 ps |
| T900 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3059406773 |
|
|
Aug 03 05:58:22 PM PDT 24 |
Aug 03 05:59:22 PM PDT 24 |
1539426744 ps |
| T901 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.733443699 |
|
|
Aug 03 05:56:02 PM PDT 24 |
Aug 03 05:56:08 PM PDT 24 |
303360499 ps |
| T902 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.125385416 |
|
|
Aug 03 05:56:24 PM PDT 24 |
Aug 03 05:56:32 PM PDT 24 |
134843330 ps |
| T903 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2091207803 |
|
|
Aug 03 06:03:49 PM PDT 24 |
Aug 03 06:08:20 PM PDT 24 |
12211732280 ps |
| T904 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.298726816 |
|
|
Aug 03 05:56:17 PM PDT 24 |
Aug 03 05:56:34 PM PDT 24 |
188496104 ps |
| T905 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.802042318 |
|
|
Aug 03 06:03:36 PM PDT 24 |
Aug 03 06:04:42 PM PDT 24 |
214208380 ps |
| T906 |
/workspace/coverage/default/26.sram_ctrl_smoke.1102239430 |
|
|
Aug 03 05:58:37 PM PDT 24 |
Aug 03 05:58:41 PM PDT 24 |
347473796 ps |
| T907 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2960955194 |
|
|
Aug 03 05:59:01 PM PDT 24 |
Aug 03 05:59:01 PM PDT 24 |
18960579 ps |
| T908 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1676902524 |
|
|
Aug 03 06:05:29 PM PDT 24 |
Aug 03 06:12:15 PM PDT 24 |
14762411421 ps |
| T909 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3527240573 |
|
|
Aug 03 06:00:52 PM PDT 24 |
Aug 03 06:00:53 PM PDT 24 |
137072436 ps |
| T910 |
/workspace/coverage/default/15.sram_ctrl_partial_access.652146498 |
|
|
Aug 03 05:55:12 PM PDT 24 |
Aug 03 05:57:06 PM PDT 24 |
898776678 ps |
| T911 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2188753267 |
|
|
Aug 03 06:00:46 PM PDT 24 |
Aug 03 06:00:46 PM PDT 24 |
12732174 ps |
| T912 |
/workspace/coverage/default/9.sram_ctrl_smoke.4185387111 |
|
|
Aug 03 05:53:51 PM PDT 24 |
Aug 03 05:54:52 PM PDT 24 |
1330618956 ps |
| T913 |
/workspace/coverage/default/20.sram_ctrl_executable.3671462135 |
|
|
Aug 03 05:56:37 PM PDT 24 |
Aug 03 06:17:38 PM PDT 24 |
163270407745 ps |
| T914 |
/workspace/coverage/default/2.sram_ctrl_regwen.1651572721 |
|
|
Aug 03 05:53:14 PM PDT 24 |
Aug 03 06:11:03 PM PDT 24 |
13749651666 ps |
| T915 |
/workspace/coverage/default/45.sram_ctrl_bijection.2451562088 |
|
|
Aug 03 06:04:27 PM PDT 24 |
Aug 03 06:05:02 PM PDT 24 |
6780355808 ps |
| T916 |
/workspace/coverage/default/42.sram_ctrl_regwen.1790946352 |
|
|
Aug 03 06:03:49 PM PDT 24 |
Aug 03 06:29:40 PM PDT 24 |
5056903587 ps |
| T917 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1612718997 |
|
|
Aug 03 05:53:32 PM PDT 24 |
Aug 03 05:53:35 PM PDT 24 |
150776399 ps |
| T918 |
/workspace/coverage/default/18.sram_ctrl_executable.4132637524 |
|
|
Aug 03 05:56:02 PM PDT 24 |
Aug 03 06:20:59 PM PDT 24 |
208165038859 ps |
| T919 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.477239634 |
|
|
Aug 03 05:53:22 PM PDT 24 |
Aug 03 06:13:52 PM PDT 24 |
2300296991 ps |
| T920 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3430608663 |
|
|
Aug 03 06:02:27 PM PDT 24 |
Aug 03 06:13:17 PM PDT 24 |
18863256659 ps |
| T921 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.818864412 |
|
|
Aug 03 05:57:01 PM PDT 24 |
Aug 03 05:57:02 PM PDT 24 |
71595873 ps |
| T922 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.919929126 |
|
|
Aug 03 05:53:38 PM PDT 24 |
Aug 03 05:55:37 PM PDT 24 |
141636847 ps |
| T923 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2744845655 |
|
|
Aug 03 05:59:12 PM PDT 24 |
Aug 03 05:59:24 PM PDT 24 |
445237747 ps |
| T924 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.512511165 |
|
|
Aug 03 05:58:50 PM PDT 24 |
Aug 03 06:08:04 PM PDT 24 |
3404729473 ps |
| T925 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2562537692 |
|
|
Aug 03 05:55:58 PM PDT 24 |
Aug 03 06:02:51 PM PDT 24 |
3112413843 ps |
| T926 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3911161870 |
|
|
Aug 03 06:02:46 PM PDT 24 |
Aug 03 06:02:47 PM PDT 24 |
326997394 ps |
| T927 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3819598905 |
|
|
Aug 03 06:00:23 PM PDT 24 |
Aug 03 06:18:58 PM PDT 24 |
39402790365 ps |
| T928 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3218191695 |
|
|
Aug 03 06:05:32 PM PDT 24 |
Aug 03 06:11:17 PM PDT 24 |
7041384864 ps |
| T929 |
/workspace/coverage/default/23.sram_ctrl_bijection.3649611449 |
|
|
Aug 03 05:57:30 PM PDT 24 |
Aug 03 05:57:57 PM PDT 24 |
4662608666 ps |
| T930 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2950277149 |
|
|
Aug 03 05:53:46 PM PDT 24 |
Aug 03 05:54:24 PM PDT 24 |
103388544 ps |
| T931 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1298022543 |
|
|
Aug 03 06:01:08 PM PDT 24 |
Aug 03 07:12:53 PM PDT 24 |
48226279523 ps |
| T932 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2009861133 |
|
|
Aug 03 05:53:17 PM PDT 24 |
Aug 03 05:53:23 PM PDT 24 |
98633100 ps |
| T933 |
/workspace/coverage/default/22.sram_ctrl_smoke.726818398 |
|
|
Aug 03 05:57:15 PM PDT 24 |
Aug 03 05:58:05 PM PDT 24 |
6101149651 ps |
| T934 |
/workspace/coverage/default/31.sram_ctrl_partial_access.4197444874 |
|
|
Aug 03 06:00:18 PM PDT 24 |
Aug 03 06:02:31 PM PDT 24 |
2515426274 ps |
| T935 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.187445528 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:25 PM PDT 24 |
496845783 ps |
| T66 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.243165629 |
|
|
Aug 03 04:24:26 PM PDT 24 |
Aug 03 04:24:27 PM PDT 24 |
47193830 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2380561406 |
|
|
Aug 03 04:24:30 PM PDT 24 |
Aug 03 04:24:32 PM PDT 24 |
219245394 ps |
| T936 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3006376566 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:22 PM PDT 24 |
232778254 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.72899428 |
|
|
Aug 03 04:25:05 PM PDT 24 |
Aug 03 04:25:09 PM PDT 24 |
1270984500 ps |
| T61 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3831681741 |
|
|
Aug 03 04:24:18 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
112051656 ps |
| T62 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2564580959 |
|
|
Aug 03 04:24:23 PM PDT 24 |
Aug 03 04:24:25 PM PDT 24 |
235300473 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.586173663 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:18 PM PDT 24 |
44210100 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4104925223 |
|
|
Aug 03 04:24:41 PM PDT 24 |
Aug 03 04:24:42 PM PDT 24 |
34796728 ps |
| T937 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2287208576 |
|
|
Aug 03 04:24:24 PM PDT 24 |
Aug 03 04:24:25 PM PDT 24 |
61094293 ps |
| T938 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4284491844 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:28 PM PDT 24 |
147273111 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.598650710 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
1420158320 ps |
| T114 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3320954647 |
|
|
Aug 03 04:24:18 PM PDT 24 |
Aug 03 04:24:19 PM PDT 24 |
62139908 ps |
| T97 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3142071900 |
|
|
Aug 03 04:24:33 PM PDT 24 |
Aug 03 04:24:34 PM PDT 24 |
86156852 ps |
| T939 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3021035977 |
|
|
Aug 03 04:24:09 PM PDT 24 |
Aug 03 04:24:11 PM PDT 24 |
58152897 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1170999185 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
518032659 ps |
| T129 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.758080300 |
|
|
Aug 03 04:24:15 PM PDT 24 |
Aug 03 04:24:17 PM PDT 24 |
221657900 ps |
| T940 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.180935312 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:29 PM PDT 24 |
138972834 ps |
| T115 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.486020966 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:26 PM PDT 24 |
31992066 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2455215869 |
|
|
Aug 03 04:24:31 PM PDT 24 |
Aug 03 04:24:35 PM PDT 24 |
1325556315 ps |
| T74 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.691587527 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:29 PM PDT 24 |
737209658 ps |
| T75 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1711288274 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:24 PM PDT 24 |
1587246717 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.852991482 |
|
|
Aug 03 04:24:47 PM PDT 24 |
Aug 03 04:24:50 PM PDT 24 |
266818603 ps |
| T76 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3851028279 |
|
|
Aug 03 04:24:24 PM PDT 24 |
Aug 03 04:24:25 PM PDT 24 |
11276272 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.853389677 |
|
|
Aug 03 04:25:01 PM PDT 24 |
Aug 03 04:25:02 PM PDT 24 |
101797707 ps |
| T941 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3524061012 |
|
|
Aug 03 04:24:36 PM PDT 24 |
Aug 03 04:24:38 PM PDT 24 |
1154970140 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3904469762 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
136043362 ps |
| T78 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.464804062 |
|
|
Aug 03 04:24:36 PM PDT 24 |
Aug 03 04:24:39 PM PDT 24 |
839887655 ps |
| T132 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.257831601 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:19 PM PDT 24 |
293580853 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2725834187 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:29 PM PDT 24 |
21245017 ps |
| T944 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.136858800 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:33 PM PDT 24 |
261411800 ps |
| T945 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3782807990 |
|
|
Aug 03 04:24:21 PM PDT 24 |
Aug 03 04:24:22 PM PDT 24 |
143848009 ps |
| T130 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1719488114 |
|
|
Aug 03 04:24:57 PM PDT 24 |
Aug 03 04:24:59 PM PDT 24 |
642491594 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3530016436 |
|
|
Aug 03 04:24:59 PM PDT 24 |
Aug 03 04:25:00 PM PDT 24 |
16924978 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2325847052 |
|
|
Aug 03 04:24:18 PM PDT 24 |
Aug 03 04:24:19 PM PDT 24 |
32865031 ps |
| T81 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1502987320 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
112862004 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3787326254 |
|
|
Aug 03 04:24:34 PM PDT 24 |
Aug 03 04:24:35 PM PDT 24 |
77859067 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.665755388 |
|
|
Aug 03 04:24:18 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
461536127 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3805598818 |
|
|
Aug 03 04:24:42 PM PDT 24 |
Aug 03 04:24:45 PM PDT 24 |
327329611 ps |
| T82 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1707147418 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:22 PM PDT 24 |
1133649807 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.431169564 |
|
|
Aug 03 04:24:57 PM PDT 24 |
Aug 03 04:25:01 PM PDT 24 |
116314446 ps |
| T137 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4076166731 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
84366035 ps |
| T950 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2947996515 |
|
|
Aug 03 04:24:23 PM PDT 24 |
Aug 03 04:24:24 PM PDT 24 |
29621424 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2047521460 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:30 PM PDT 24 |
259194212 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2290570701 |
|
|
Aug 03 04:24:33 PM PDT 24 |
Aug 03 04:24:37 PM PDT 24 |
447491504 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.537486786 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:18 PM PDT 24 |
32857541 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2668041485 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:30 PM PDT 24 |
326508860 ps |
| T90 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.914912243 |
|
|
Aug 03 04:24:27 PM PDT 24 |
Aug 03 04:24:30 PM PDT 24 |
484527886 ps |
| T955 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1621089798 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
97043383 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1064016233 |
|
|
Aug 03 04:24:30 PM PDT 24 |
Aug 03 04:24:31 PM PDT 24 |
43631473 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3227799908 |
|
|
Aug 03 04:24:41 PM PDT 24 |
Aug 03 04:24:42 PM PDT 24 |
39648740 ps |
| T136 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2425552082 |
|
|
Aug 03 04:24:38 PM PDT 24 |
Aug 03 04:24:40 PM PDT 24 |
155663582 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3728410463 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
44461607 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2407574219 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:23 PM PDT 24 |
669000544 ps |
| T959 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1322615444 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:26 PM PDT 24 |
85784726 ps |
| T960 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.821082284 |
|
|
Aug 03 04:24:54 PM PDT 24 |
Aug 03 04:24:55 PM PDT 24 |
23770072 ps |
| T134 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.547524639 |
|
|
Aug 03 04:24:50 PM PDT 24 |
Aug 03 04:24:52 PM PDT 24 |
259529904 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2456646937 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
43935406 ps |
| T962 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.402737026 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:30 PM PDT 24 |
70315238 ps |
| T963 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3648249922 |
|
|
Aug 03 04:24:30 PM PDT 24 |
Aug 03 04:24:31 PM PDT 24 |
16739315 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.900071583 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
30347316 ps |
| T965 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.443688722 |
|
|
Aug 03 04:24:16 PM PDT 24 |
Aug 03 04:24:16 PM PDT 24 |
67672510 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2373921690 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:30 PM PDT 24 |
252538696 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2816007589 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
27384170 ps |
| T92 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1493893145 |
|
|
Aug 03 04:24:41 PM PDT 24 |
Aug 03 04:24:46 PM PDT 24 |
6155355957 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2827034586 |
|
|
Aug 03 04:24:30 PM PDT 24 |
Aug 03 04:24:32 PM PDT 24 |
102921765 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3416549465 |
|
|
Aug 03 04:24:31 PM PDT 24 |
Aug 03 04:24:31 PM PDT 24 |
24061360 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3513450683 |
|
|
Aug 03 04:24:27 PM PDT 24 |
Aug 03 04:24:28 PM PDT 24 |
78381737 ps |
| T971 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2919886766 |
|
|
Aug 03 04:24:55 PM PDT 24 |
Aug 03 04:24:58 PM PDT 24 |
466241377 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1382809399 |
|
|
Aug 03 04:24:13 PM PDT 24 |
Aug 03 04:24:17 PM PDT 24 |
35546334 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3146524942 |
|
|
Aug 03 04:24:21 PM PDT 24 |
Aug 03 04:24:23 PM PDT 24 |
124644249 ps |
| T138 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1724586630 |
|
|
Aug 03 04:24:35 PM PDT 24 |
Aug 03 04:24:36 PM PDT 24 |
92251170 ps |
| T974 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4158957679 |
|
|
Aug 03 04:24:18 PM PDT 24 |
Aug 03 04:24:19 PM PDT 24 |
29080956 ps |
| T975 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.637343602 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:29 PM PDT 24 |
28281975 ps |
| T976 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.504270731 |
|
|
Aug 03 04:24:33 PM PDT 24 |
Aug 03 04:24:36 PM PDT 24 |
66061813 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3334617301 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:21 PM PDT 24 |
86176242 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3793359972 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:19 PM PDT 24 |
123614715 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2424478716 |
|
|
Aug 03 04:24:50 PM PDT 24 |
Aug 03 04:24:51 PM PDT 24 |
114496987 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3923072254 |
|
|
Aug 03 04:24:54 PM PDT 24 |
Aug 03 04:24:55 PM PDT 24 |
24663635 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1185614256 |
|
|
Aug 03 04:24:15 PM PDT 24 |
Aug 03 04:24:16 PM PDT 24 |
20017178 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2345315582 |
|
|
Aug 03 04:24:18 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
96008179 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2237654069 |
|
|
Aug 03 04:24:40 PM PDT 24 |
Aug 03 04:24:40 PM PDT 24 |
16601733 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.638901173 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:31 PM PDT 24 |
26595937 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2900276408 |
|
|
Aug 03 04:24:28 PM PDT 24 |
Aug 03 04:24:29 PM PDT 24 |
49239362 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3330488626 |
|
|
Aug 03 04:24:19 PM PDT 24 |
Aug 03 04:24:23 PM PDT 24 |
58248018 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.873419378 |
|
|
Aug 03 04:25:01 PM PDT 24 |
Aug 03 04:25:02 PM PDT 24 |
12878408 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1283019066 |
|
|
Aug 03 04:24:21 PM PDT 24 |
Aug 03 04:24:22 PM PDT 24 |
37244222 ps |
| T986 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2097389328 |
|
|
Aug 03 04:24:31 PM PDT 24 |
Aug 03 04:24:34 PM PDT 24 |
90255397 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3725705885 |
|
|
Aug 03 04:24:20 PM PDT 24 |
Aug 03 04:24:20 PM PDT 24 |
25830844 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1831219278 |
|
|
Aug 03 04:24:26 PM PDT 24 |
Aug 03 04:24:27 PM PDT 24 |
44350125 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.407657336 |
|
|
Aug 03 04:24:16 PM PDT 24 |
Aug 03 04:24:17 PM PDT 24 |
49898876 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1405671605 |
|
|
Aug 03 04:24:24 PM PDT 24 |
Aug 03 04:24:25 PM PDT 24 |
14362322 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2741105076 |
|
|
Aug 03 04:24:55 PM PDT 24 |
Aug 03 04:24:58 PM PDT 24 |
383723612 ps |
| T135 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3135374941 |
|
|
Aug 03 04:24:32 PM PDT 24 |
Aug 03 04:24:34 PM PDT 24 |
674165567 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2618593566 |
|
|
Aug 03 04:24:38 PM PDT 24 |
Aug 03 04:24:42 PM PDT 24 |
116756492 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1708324070 |
|
|
Aug 03 04:24:22 PM PDT 24 |
Aug 03 04:24:22 PM PDT 24 |
20262199 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.267150105 |
|
|
Aug 03 04:24:17 PM PDT 24 |
Aug 03 04:24:19 PM PDT 24 |
180203772 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1135040745 |
|
|
Aug 03 04:24:25 PM PDT 24 |
Aug 03 04:24:26 PM PDT 24 |
29197141 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2543975727 |
|
|
Aug 03 04:24:22 PM PDT 24 |
Aug 03 04:24:24 PM PDT 24 |
293860707 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2192523339 |
|
|
Aug 03 04:24:37 PM PDT 24 |
Aug 03 04:24:40 PM PDT 24 |
442167344 ps |
| T998 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.284451636 |
|
|
Aug 03 04:24:26 PM PDT 24 |
Aug 03 04:24:27 PM PDT 24 |
30893235 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.855720608 |
|
|
Aug 03 04:24:55 PM PDT 24 |
Aug 03 04:24:56 PM PDT 24 |
23695292 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.226649872 |
|
|
Aug 03 04:24:23 PM PDT 24 |
Aug 03 04:24:24 PM PDT 24 |
1512756194 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3721786703 |
|
|
Aug 03 04:24:11 PM PDT 24 |
Aug 03 04:24:14 PM PDT 24 |
381162167 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.42750462 |
|
|
Aug 03 04:24:14 PM PDT 24 |
Aug 03 04:24:16 PM PDT 24 |
452267267 ps |
| T1002 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1334268628 |
|
|
Aug 03 04:24:14 PM PDT 24 |
Aug 03 04:24:17 PM PDT 24 |
132195260 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.861689557 |
|
|
Aug 03 04:24:16 PM PDT 24 |
Aug 03 04:24:16 PM PDT 24 |
43893696 ps |