Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14670209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56372877

1

T1

841

T2

42326

T3

8160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35414979	1			T1	392		T2	117209		T3	4184
values[0x0]	16347257	1			T1	227		T2	39090		T3	1987
values[0x1]	19280850	1			T1	222		T2	77210		T3	1989

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7311602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63731484

1

T1

841

T2

138411

T3

8160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	254491	1			T2	932		T4	1504		T5	12
valid_sources[0x01]	254477	1			T2	854		T4	1295		T5	21
valid_sources[0x02]	255383	1			T2	875		T4	1398		T5	14
valid_sources[0x03]	286403	1			T2	886		T4	1421		T5	15
valid_sources[0x04]	249289	1			T2	901		T4	1316		T5	13
valid_sources[0x05]	260865	1			T2	859		T4	1341		T5	10
valid_sources[0x06]	354076	1			T2	880		T4	1306		T5	25
valid_sources[0x07]	289789	1			T2	805		T4	1233		T5	13
valid_sources[0x08]	251326	1			T2	996		T4	1140		T5	10
valid_sources[0x09]	261378	1			T2	774		T4	1280		T5	20
valid_sources[0x0a]	245553	1			T2	874		T4	1242		T5	23
valid_sources[0x0b]	279812	1			T2	824		T4	1394		T5	14
valid_sources[0x0c]	252470	1			T2	924		T4	1417		T5	14
valid_sources[0x0d]	274474	1			T2	967		T3	4080		T4	1282
valid_sources[0x0e]	258330	1			T2	925		T4	1403		T5	10
valid_sources[0x0f]	268738	1			T2	979		T4	1330		T5	9
valid_sources[0x10]	273791	1			T2	987		T4	1332		T5	9
valid_sources[0x11]	331489	1			T2	908		T4	1479		T5	7
valid_sources[0x12]	252030	1			T2	924		T4	1448		T5	23
valid_sources[0x13]	281785	1			T2	855		T4	1376		T5	4
valid_sources[0x14]	310313	1			T2	949		T4	1382		T5	13
valid_sources[0x15]	283278	1			T2	858		T4	1239		T5	17
valid_sources[0x16]	272472	1			T2	862		T4	1266		T5	8
valid_sources[0x17]	260325	1			T2	861		T4	1274		T5	12
valid_sources[0x18]	263216	1			T2	916		T4	1408		T5	17
valid_sources[0x19]	276692	1			T2	965		T4	1393		T5	13
valid_sources[0x1a]	281322	1			T2	931		T4	1323		T5	5
valid_sources[0x1b]	284749	1			T2	953		T4	1156		T5	13
valid_sources[0x1c]	297533	1			T2	963		T4	1392		T5	8
valid_sources[0x1d]	253071	1			T2	924		T4	1277		T5	12
valid_sources[0x1e]	315496	1			T2	865		T4	1242		T5	18
valid_sources[0x1f]	264900	1			T2	1013		T4	1339		T5	16
valid_sources[0x20]	291055	1			T2	812		T4	1308		T5	10
valid_sources[0x21]	248202	1			T2	893		T4	1233		T5	14
valid_sources[0x22]	338242	1			T2	970		T4	1353		T5	18
valid_sources[0x23]	271631	1			T2	873		T4	1577		T5	12
valid_sources[0x24]	259400	1			T2	1103		T4	1288		T5	18
valid_sources[0x25]	287416	1			T2	1039		T4	1502		T5	13
valid_sources[0x26]	274717	1			T2	822		T4	1470		T5	10
valid_sources[0x27]	278516	1			T2	962		T4	1397		T5	4
valid_sources[0x28]	275004	1			T2	868		T4	1264		T5	7
valid_sources[0x29]	259665	1			T2	761		T4	1290		T5	6
valid_sources[0x2a]	265207	1			T2	926		T3	4080		T4	1369
valid_sources[0x2b]	281583	1			T2	745		T4	1297		T5	2
valid_sources[0x2c]	293035	1			T2	851		T4	1210		T5	32
valid_sources[0x2d]	267465	1			T2	1030		T4	1283		T5	10
valid_sources[0x2e]	281063	1			T2	859		T4	1167		T5	5
valid_sources[0x2f]	285263	1			T2	956		T4	1278		T5	4
valid_sources[0x30]	288927	1			T2	905		T4	1311		T5	6
valid_sources[0x31]	265285	1			T2	975		T4	1517		T5	8
valid_sources[0x32]	250432	1			T2	940		T4	1418		T5	8
valid_sources[0x33]	266087	1			T2	810		T4	1405		T5	9
valid_sources[0x34]	255971	1			T2	865		T4	1265		T5	19
valid_sources[0x35]	253777	1			T2	970		T4	1264		T5	3
valid_sources[0x36]	258658	1			T2	883		T4	1336		T5	14
valid_sources[0x37]	246795	1			T2	1095		T4	1251		T5	12
valid_sources[0x38]	300215	1			T2	902		T4	1253		T5	1
valid_sources[0x39]	245849	1			T2	899		T4	1283		T5	17
valid_sources[0x3a]	353326	1			T2	822		T4	1350		T5	9
valid_sources[0x3b]	277178	1			T2	849		T4	1305		T5	12
valid_sources[0x3c]	330158	1			T2	846		T4	1328		T5	17
valid_sources[0x3d]	266646	1			T2	933		T4	1375		T5	20
valid_sources[0x3e]	283794	1			T2	886		T4	1355		T5	12
valid_sources[0x3f]	279472	1			T2	828		T4	1312		T8	5000
valid_sources[0x40]	265689	1			T2	997		T4	1393		T5	8
valid_sources[0x41]	299641	1			T2	1012		T4	1322		T5	13
valid_sources[0x42]	259501	1			T2	868		T4	1370		T5	15
valid_sources[0x43]	295471	1			T2	1062		T4	1438		T5	4
valid_sources[0x44]	257392	1			T2	964		T4	1457		T5	10
valid_sources[0x45]	279581	1			T2	1099		T4	1298		T5	20
valid_sources[0x46]	270481	1			T2	857		T4	1282		T5	13
valid_sources[0x47]	327161	1			T2	929		T4	1381		T5	15
valid_sources[0x48]	279940	1			T2	796		T4	1210		T5	18
valid_sources[0x49]	280252	1			T2	853		T4	1448		T5	15
valid_sources[0x4a]	256315	1			T2	927		T4	1160		T5	6
valid_sources[0x4b]	265099	1			T2	765		T4	1413		T5	8
valid_sources[0x4c]	266672	1			T2	875		T4	1324		T5	14
valid_sources[0x4d]	321815	1			T2	811		T4	1307		T5	4
valid_sources[0x4e]	285613	1			T2	983		T4	1384		T5	3
valid_sources[0x4f]	262062	1			T2	877		T4	1439		T5	20
valid_sources[0x50]	304390	1			T2	884		T4	1175		T5	5
valid_sources[0x51]	271841	1			T2	762		T4	1355		T5	17
valid_sources[0x52]	246912	1			T2	913		T4	1331		T5	19
valid_sources[0x53]	326601	1			T2	796		T4	1352		T5	12
valid_sources[0x54]	272665	1			T2	1008		T4	1344		T5	7
valid_sources[0x55]	256827	1			T2	866		T4	1298		T5	16
valid_sources[0x56]	259047	1			T2	987		T4	1374		T5	11
valid_sources[0x57]	308218	1			T2	906		T4	1207		T5	2
valid_sources[0x58]	246645	1			T2	951		T4	1411		T5	5
valid_sources[0x59]	343031	1			T2	914		T4	1406		T5	9
valid_sources[0x5a]	290486	1			T2	892		T4	1379		T5	6
valid_sources[0x5b]	271066	1			T2	878		T4	1380		T5	9
valid_sources[0x5c]	285198	1			T2	1028		T4	1221		T5	14
valid_sources[0x5d]	253227	1			T2	907		T4	1262		T5	15
valid_sources[0x5e]	261903	1			T2	881		T4	1284		T5	12
valid_sources[0x5f]	250106	1			T2	915		T4	1275		T5	11
valid_sources[0x60]	362061	1			T2	862		T4	1329		T5	10
valid_sources[0x61]	263785	1			T2	1054		T4	1384		T5	9
valid_sources[0x62]	291510	1			T2	880		T4	1398		T5	24
valid_sources[0x63]	290063	1			T2	897		T4	1305		T5	22
valid_sources[0x64]	255846	1			T2	1111		T4	1235		T5	23
valid_sources[0x65]	337254	1			T1	420		T2	990		T4	1357
valid_sources[0x66]	274538	1			T2	980		T4	1417		T5	10
valid_sources[0x67]	247145	1			T2	935		T4	1176		T5	15
valid_sources[0x68]	287308	1			T2	924		T4	1302		T5	12
valid_sources[0x69]	250156	1			T2	805		T4	1408		T5	12
valid_sources[0x6a]	294025	1			T2	936		T4	1385		T5	4
valid_sources[0x6b]	247604	1			T2	867		T4	1327		T5	10
valid_sources[0x6c]	340833	1			T2	957		T4	1367		T5	17
valid_sources[0x6d]	251920	1			T2	872		T4	1283		T5	2
valid_sources[0x6e]	275193	1			T2	954		T4	1341		T5	4
valid_sources[0x6f]	261186	1			T2	1012		T4	1366		T5	5
valid_sources[0x70]	282964	1			T2	801		T4	1277		T5	16
valid_sources[0x71]	248988	1			T2	947		T4	1263		T5	11
valid_sources[0x72]	286725	1			T2	999		T4	1218		T5	12
valid_sources[0x73]	275579	1			T2	745		T4	1354		T5	19
valid_sources[0x74]	307953	1			T2	922		T4	1371		T5	12
valid_sources[0x75]	259523	1			T2	864		T4	1203		T5	10
valid_sources[0x76]	297126	1			T2	882		T4	1397		T5	10
valid_sources[0x77]	250296	1			T2	935		T4	1529		T5	24
valid_sources[0x78]	253674	1			T2	880		T4	1298		T5	25
valid_sources[0x79]	336430	1			T2	981		T4	1520		T5	17
valid_sources[0x7a]	343767	1			T2	854		T4	1318		T5	5
valid_sources[0x7b]	294607	1			T2	1006		T4	1395		T5	9
valid_sources[0x7c]	261839	1			T2	1040		T4	1539		T5	13
valid_sources[0x7d]	267150	1			T2	798		T4	1441		T5	10
valid_sources[0x7e]	283105	1			T2	907		T4	1347		T5	22
valid_sources[0x7f]	273420	1			T2	912		T4	1346		T5	10
valid_sources[0x80]	263164	1			T2	903		T4	1299		T5	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28084223

1

T1

392

T2

21186

T3

4184

values[0x0]

all_enables

biggest_size

14144516

1

T1

227

T2

10559

T3

1987

values[0x1]

all_enables

biggest_size

14144138

1

T1

222

T2

10581

T3

1989

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140689

1

T1

1

T2

2

T4

87

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51256	1			T4	87		T6	29		T25	495
values[0x0]	60408	1			T1	2		T2	5		T3	2
values[0x1]	65049	1			T2	3		T4	66		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149724

1

T1

1

T2

2

T4

102

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	775	1			T4	1		T25	2		T21	12
valid_sources[0x01]	580	1			T4	1		T25	9		T7	1
valid_sources[0x02]	679	1			T4	2		T6	1		T25	9
valid_sources[0x03]	735	1			T4	4		T6	1		T25	8
valid_sources[0x04]	612	1			T4	1		T25	6		T21	8
valid_sources[0x05]	491	1			T4	1		T25	3		T21	11
valid_sources[0x06]	614	1			T4	2		T25	8		T7	1
valid_sources[0x07]	827	1			T25	10		T7	3		T21	8
valid_sources[0x08]	730	1			T4	1		T25	7		T21	4
valid_sources[0x09]	623	1			T4	1		T25	1		T26	6
valid_sources[0x0a]	704	1			T25	7		T21	2		T26	24
valid_sources[0x0b]	658	1			T25	4		T7	1		T21	18
valid_sources[0x0c]	788	1			T4	1		T25	2		T21	9
valid_sources[0x0d]	567	1			T4	2		T25	7		T7	1
valid_sources[0x0e]	556	1			T25	10		T21	7		T26	1
valid_sources[0x0f]	622	1			T4	1		T25	12		T7	1
valid_sources[0x10]	743	1			T25	7		T7	3		T26	10
valid_sources[0x11]	866	1			T25	6		T7	3		T21	1
valid_sources[0x12]	613	1			T25	22		T21	11		T26	9
valid_sources[0x13]	997	1			T44	1		T25	7		T49	1
valid_sources[0x14]	661	1			T25	8		T21	3		T26	7
valid_sources[0x15]	803	1			T4	1		T25	6		T21	2
valid_sources[0x16]	878	1			T25	7		T59	9		T7	5
valid_sources[0x17]	802	1			T6	1		T25	1		T21	18
valid_sources[0x18]	820	1			T2	3		T4	1		T25	6
valid_sources[0x19]	550	1			T4	1		T25	10		T92	1
valid_sources[0x1a]	597	1			T4	2		T25	7		T21	25
valid_sources[0x1b]	760	1			T4	3		T25	14		T21	19
valid_sources[0x1c]	773	1			T4	1		T25	2		T14	3
valid_sources[0x1d]	719	1			T4	1		T25	5		T59	1
valid_sources[0x1e]	565	1			T4	1		T25	14		T7	1
valid_sources[0x1f]	744	1			T4	1		T25	9		T21	21
valid_sources[0x20]	717	1			T4	1		T25	5		T7	1
valid_sources[0x21]	590	1			T4	1		T25	5		T43	4
valid_sources[0x22]	989	1			T4	1		T6	1		T25	14
valid_sources[0x23]	571	1			T4	1		T25	7		T7	3
valid_sources[0x24]	775	1			T25	17		T21	13		T26	2
valid_sources[0x25]	600	1			T4	3		T25	14		T123	2
valid_sources[0x26]	733	1			T4	1		T25	5		T21	11
valid_sources[0x27]	671	1			T4	2		T25	5		T21	6
valid_sources[0x28]	586	1			T4	1		T25	7		T21	26
valid_sources[0x29]	779	1			T4	1		T20	1		T25	7
valid_sources[0x2a]	642	1			T6	1		T25	10		T7	1
valid_sources[0x2b]	606	1			T4	1		T25	1		T45	1
valid_sources[0x2c]	598	1			T4	1		T25	12		T7	2
valid_sources[0x2d]	634	1			T25	6		T21	6		T26	5
valid_sources[0x2e]	553	1			T20	5		T25	3		T21	13
valid_sources[0x2f]	718	1			T4	1		T25	6		T21	21
valid_sources[0x30]	982	1			T4	1		T25	3		T7	2
valid_sources[0x31]	636	1			T25	5		T21	4		T26	8
valid_sources[0x32]	696	1			T4	2		T25	4		T21	9
valid_sources[0x33]	555	1			T4	1		T25	6		T49	1
valid_sources[0x34]	706	1			T25	4		T21	10		T26	28
valid_sources[0x35]	612	1			T4	1		T25	15		T21	21
valid_sources[0x36]	560	1			T4	1		T25	5		T59	5
valid_sources[0x37]	753	1			T6	4		T25	9		T21	4
valid_sources[0x38]	660	1			T4	2		T5	1		T25	6
valid_sources[0x39]	916	1			T25	8		T49	1		T21	12
valid_sources[0x3a]	551	1			T4	1		T6	1		T25	4
valid_sources[0x3b]	681	1			T25	13		T29	1		T21	11
valid_sources[0x3c]	621	1			T4	1		T25	7		T21	14
valid_sources[0x3d]	787	1			T4	1		T25	12		T49	2
valid_sources[0x3e]	692	1			T5	1		T25	10		T21	5
valid_sources[0x3f]	675	1			T4	2		T25	5		T7	3
valid_sources[0x40]	574	1			T4	1		T25	6		T21	8
valid_sources[0x41]	608	1			T4	1		T25	12		T7	1
valid_sources[0x42]	692	1			T9	2		T25	6		T21	1
valid_sources[0x43]	662	1			T25	8		T21	9		T26	23
valid_sources[0x44]	664	1			T4	1		T25	2		T21	4
valid_sources[0x45]	580	1			T25	4		T7	1		T49	1
valid_sources[0x46]	719	1			T4	1		T25	7		T7	4
valid_sources[0x47]	761	1			T4	1		T25	7		T7	1
valid_sources[0x48]	862	1			T25	8		T21	5		T26	16
valid_sources[0x49]	599	1			T4	2		T25	1		T59	2
valid_sources[0x4a]	490	1			T25	5		T21	16		T97	1
valid_sources[0x4b]	651	1			T6	4		T25	8		T21	13
valid_sources[0x4c]	709	1			T4	1		T6	1		T25	12
valid_sources[0x4d]	915	1			T25	4		T26	24		T72	5
valid_sources[0x4e]	862	1			T4	2		T25	5		T21	19
valid_sources[0x4f]	596	1			T4	1		T25	10		T21	20
valid_sources[0x50]	526	1			T25	7		T21	5		T26	25
valid_sources[0x51]	491	1			T4	1		T25	8		T7	3
valid_sources[0x52]	960	1			T4	1		T25	5		T21	23
valid_sources[0x53]	848	1			T4	1		T25	6		T49	1
valid_sources[0x54]	719	1			T6	1		T25	17		T21	27
valid_sources[0x55]	654	1			T25	7		T21	30		T26	10
valid_sources[0x56]	809	1			T1	1		T4	1		T25	6
valid_sources[0x57]	641	1			T4	1		T25	9		T21	10
valid_sources[0x58]	770	1			T4	2		T6	2		T25	12
valid_sources[0x59]	723	1			T25	8		T7	1		T93	5
valid_sources[0x5a]	593	1			T6	2		T25	2		T21	9
valid_sources[0x5b]	656	1			T4	3		T25	4		T21	2
valid_sources[0x5c]	782	1			T4	1		T25	15		T59	1
valid_sources[0x5d]	605	1			T4	1		T25	4		T68	2
valid_sources[0x5e]	919	1			T4	2		T25	9		T59	4
valid_sources[0x5f]	540	1			T25	8		T49	1		T21	2
valid_sources[0x60]	507	1			T4	3		T25	8		T21	13
valid_sources[0x61]	778	1			T4	1		T25	4		T21	16
valid_sources[0x62]	1053	1			T2	3		T4	1		T25	9
valid_sources[0x63]	544	1			T4	2		T25	7		T7	3
valid_sources[0x64]	581	1			T4	1		T25	3		T21	7
valid_sources[0x65]	717	1			T2	1		T4	1		T25	4
valid_sources[0x66]	801	1			T25	6		T21	10		T26	14
valid_sources[0x67]	720	1			T6	1		T25	7		T92	1
valid_sources[0x68]	462	1			T44	1		T25	4		T21	4
valid_sources[0x69]	791	1			T4	1		T10	2		T6	3
valid_sources[0x6a]	629	1			T4	1		T6	1		T25	5
valid_sources[0x6b]	710	1			T25	13		T7	2		T49	1
valid_sources[0x6c]	619	1			T4	2		T44	1		T25	12
valid_sources[0x6d]	640	1			T6	1		T25	8		T7	2
valid_sources[0x6e]	491	1			T4	1		T25	5		T21	8
valid_sources[0x6f]	823	1			T4	1		T25	6		T21	7
valid_sources[0x70]	593	1			T4	4		T25	6		T49	3
valid_sources[0x71]	588	1			T4	1		T25	4		T49	1
valid_sources[0x72]	745	1			T4	2		T6	2		T25	12
valid_sources[0x73]	767	1			T4	1		T25	10		T21	17
valid_sources[0x74]	748	1			T4	2		T25	8		T21	14
valid_sources[0x75]	688	1			T4	1		T25	11		T7	4
valid_sources[0x76]	609	1			T4	4		T25	9		T21	12
valid_sources[0x77]	624	1			T25	6		T21	5		T26	9
valid_sources[0x78]	916	1			T25	6		T7	3		T21	11
valid_sources[0x79]	541	1			T4	3		T25	7		T7	2
valid_sources[0x7a]	630	1			T25	12		T7	1		T21	9
valid_sources[0x7b]	1048	1			T25	11		T21	3		T97	2
valid_sources[0x7c]	655	1			T25	9		T7	1		T21	17
valid_sources[0x7d]	743	1			T4	1		T25	7		T21	17
valid_sources[0x7e]	544	1			T4	2		T25	15		T49	2
valid_sources[0x7f]	558	1			T4	2		T25	6		T7	1
valid_sources[0x80]	544	1			T4	1		T6	1		T25	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38545

1

T4

54

T6

12

T25

454

values[0x0]

all_enables

biggest_size

52159

1

T1

1

T2

2

T4

20

values[0x1]

all_enables

biggest_size

49985

1

T4

13

T9

1

T10

1