Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14370465

1

T2

191183

T4

26235

T12

890

full_word

51432912

1

T1

841

T2

42326

T3

8160

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65803077	1			T1	841		T2	233509		T3	8160
auto[TlIntgErrCmd]	100	1			T69	7		T70	3		T71	6
auto[TlIntgErrData]	109	1			T69	6		T70	10		T71	3
auto[TlIntgErrBoth]	91	1			T69	7		T70	7		T71	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30098530

1

T1

392

T2

117209

T3

4184

auto[1]

35704847

1

T1

449

T2

116300

T3

3976

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6883883	1			T2	96023		T4	13281		T12	428
auto[TlIntgErrNone]	partial	auto[1]	7486301	1			T2	95160		T4	12954		T12	462
auto[TlIntgErrNone]	full_word	auto[0]	23214511	1			T1	392		T2	21186		T3	4184
auto[TlIntgErrNone]	full_word	auto[1]	28218382	1			T1	449		T2	21140		T3	3976
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T69	4		T71	4		T142	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T69	3		T70	2		T71	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T149	1		T150	1		T151	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T70	1		T152	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T69	3		T70	5		T71	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T69	2		T70	4		T142	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T69	1		T70	1		T152	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T152	1		T154	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T69	3		T70	2		T71	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T69	4		T70	4		T142	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T70	1		T153	1		T154	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T150	1		-	-		-	-