Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	704217	1			T2	14727		T12	25		T6	1
auto[1]	10255681	1			T1	392		T2	15611		T3	4184
auto[2]	565483	1			T2	14544		T12	16		T6	1
auto[3]	10123451	1			T1	448		T2	15347		T3	3975

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13680538	1			T1	840		T2	1211		T3	8159
auto[1]	2092541	1			T2	6337		T4	10470		T12	70
auto[2]	2111005	1			T2	8483		T4	10705		T12	106
auto[3]	3764748	1			T2	44198		T4	1006		T12	17

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8081030

1

T1

840

T2

6

T3

8154

auto[1]

13567802

1

T2

60223

T3

5

T4

129

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	215717	1			T12	19		T27	21		T92	301
auto[0]	auto[0]	auto[1]	22490	1			T2	1		T12	2		T27	3
auto[0]	auto[0]	auto[2]	22357	1			T12	4		T6	1		T27	4
auto[0]	auto[0]	auto[3]	7200	1			T2	1		T92	2		T123	4
auto[0]	auto[1]	auto[0]	3102042	1			T1	392		T3	4182		T4	55436
auto[0]	auto[1]	auto[1]	324025	1			T4	4905		T12	46		T44	6
auto[0]	auto[1]	auto[2]	315804	1			T4	5733		T12	30		T6	1
auto[0]	auto[1]	auto[3]	70369	1			T2	1		T4	511		T12	4
auto[0]	auto[2]	auto[0]	179596	1			T2	1		T6	1		T92	289
auto[0]	auto[2]	auto[1]	18457	1			T92	25		T28	154		T24	1
auto[0]	auto[2]	auto[2]	21660	1			T12	11		T27	16		T92	27
auto[0]	auto[2]	auto[3]	5880	1			T12	5		T27	2		T123	6
auto[0]	auto[3]	auto[0]	3066346	1			T1	448		T3	3972		T4	55450
auto[0]	auto[3]	auto[1]	312646	1			T4	5549		T12	22		T6	1
auto[0]	auto[3]	auto[2]	325513	1			T2	1		T4	4965		T12	61
auto[0]	auto[3]	auto[3]	70928	1			T2	1		T4	495		T12	8
auto[1]	auto[0]	auto[0]	14533	1			T2	504		T43	1079		T93	129
auto[1]	auto[0]	auto[1]	64817	1			T2	2189		T43	5033		T93	589
auto[1]	auto[0]	auto[2]	64473	1			T2	2128		T43	4977		T93	601
auto[1]	auto[0]	auto[3]	292630	1			T2	9904		T43	23030		T93	2754
auto[1]	auto[1]	auto[0]	3549538	1			T2	321		T3	2		T4	62
auto[1]	auto[1]	auto[1]	670231	1			T2	2404		T4	7		T44	18482
auto[1]	auto[1]	auto[2]	650921	1			T2	1384		T4	3		T44	20291
auto[1]	auto[1]	auto[3]	1572751	1			T2	11501		T44	83531		T59	1
auto[1]	auto[2]	auto[0]	10676	1			T2	285		T43	1031		T123	832
auto[1]	auto[2]	auto[1]	47097	1			T2	1246		T43	4651		T123	3741
auto[1]	auto[2]	auto[2]	50955	1			T2	2314		T43	3314		T93	518
auto[1]	auto[2]	auto[3]	231162	1			T2	10698		T43	15384		T93	2384
auto[1]	auto[3]	auto[0]	3542090	1			T2	100		T3	3		T4	44
auto[1]	auto[3]	auto[1]	632778	1			T2	497		T4	9		T44	20278
auto[1]	auto[3]	auto[2]	659322	1			T2	2656		T4	4		T44	18262
auto[1]	auto[3]	auto[3]	1513828	1			T2	12092		T44	82838		T7	1