Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	313681482	205051	0	0
ctrl_regwen_rd_A	313681482	4362	0	0
exec_rd_A	313681482	4373	0	0
exec_regwen_rd_A	313681482	4627	0	0
readback_rd_A	313681482	2840	0	0
readback_regwen_rd_A	313681482	2277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313681482	205051	0	0
T7	443899	0	0	0
T13	1097	0	0	0
T21	0	3981	0	0
T25	57665	2308	0	0
T26	0	5783	0	0
T27	125316	0	0	0
T42	0	4350	0	0
T43	229353	0	0	0
T45	93343	0	0	0
T59	372367	0	0	0
T63	0	2550	0	0
T64	0	1702	0	0
T66	6274	0	0	0
T67	12541	0	0	0
T68	13358	0	0	0
T77	0	16462	0	0
T78	0	6413	0	0
T79	0	2597	0	0
T80	0	2233	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313681482	4362	0	0
T51	172645	432	0	0
T52	0	215	0	0
T125	270510	336	0	0
T126	0	42	0	0
T127	0	225	0	0
T128	0	157	0	0
T129	0	101	0	0
T130	0	280	0	0
T131	0	93	0	0
T132	0	205	0	0
T133	365892	0	0	0
T134	3137	0	0	0
T135	10629	0	0	0
T136	3788	0	0	0
T137	103119	0	0	0
T138	770535	0	0	0
T139	17051	0	0	0
T140	773319	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313681482	4373	0	0
T51	172645	402	0	0
T52	0	200	0	0
T125	270510	313	0	0
T126	0	80	0	0
T127	0	208	0	0
T128	0	215	0	0
T129	0	102	0	0
T130	0	308	0	0
T131	0	73	0	0
T132	0	268	0	0
T133	365892	0	0	0
T134	3137	0	0	0
T135	10629	0	0	0
T136	3788	0	0	0
T137	103119	0	0	0
T138	770535	0	0	0
T139	17051	0	0	0
T140	773319	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313681482	4627	0	0
T51	172645	411	0	0
T52	0	228	0	0
T125	270510	389	0	0
T126	0	46	0	0
T127	0	285	0	0
T128	0	166	0	0
T129	0	68	0	0
T130	0	279	0	0
T131	0	83	0	0
T132	0	306	0	0
T133	365892	0	0	0
T134	3137	0	0	0
T135	10629	0	0	0
T136	3788	0	0	0
T137	103119	0	0	0
T138	770535	0	0	0
T139	17051	0	0	0
T140	773319	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313681482	2840	0	0
T51	172645	481	0	0
T52	0	224	0	0
T125	270510	373	0	0
T126	0	30	0	0
T127	0	215	0	0
T128	0	120	0	0
T129	0	41	0	0
T130	0	239	0	0
T131	0	121	0	0
T132	0	284	0	0
T133	365892	0	0	0
T134	3137	0	0	0
T135	10629	0	0	0
T136	3788	0	0	0
T137	103119	0	0	0
T138	770535	0	0	0
T139	17051	0	0	0
T140	773319	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313681482	2277	0	0
T51	172645	368	0	0
T52	0	170	0	0
T125	270510	370	0	0
T126	0	51	0	0
T127	0	145	0	0
T128	0	126	0	0
T129	0	120	0	0
T130	0	188	0	0
T131	0	78	0	0
T132	0	232	0	0
T133	365892	0	0	0
T134	3137	0	0	0
T135	10629	0	0	0
T136	3788	0	0	0
T137	103119	0	0	0
T138	770535	0	0	0
T139	17051	0	0	0
T140	773319	0	0	0