Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13609449

1

T2

1904

T3

1871

T4

2904

full_word

52155557

1

T1

3093

T2

127

T3

88

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65764726	1			T1	3093		T2	2031		T3	1959
auto[TlIntgErrCmd]	89	1			T47	2		T48	4		T49	5
auto[TlIntgErrData]	98	1			T47	5		T48	4		T49	2
auto[TlIntgErrBoth]	93	1			T47	3		T48	2		T49	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30285413

1

T1

1570

T2

885

T3

866

auto[1]

35479593

1

T1

1523

T2

1146

T3

1093

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6528159	1			T2	878		T3	862		T4	1470
auto[TlIntgErrNone]	partial	auto[1]	7081033	1			T2	1026		T3	1009		T4	1434
auto[TlIntgErrNone]	full_word	auto[0]	23757131	1			T1	1570		T2	7		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	28398403	1			T1	1523		T2	120		T3	84
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T47	1		T48	3		T49	4
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T47	1		T48	1		T49	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T116	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T119	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T47	4		T48	2		T117	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T47	1		T48	2		T49	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T120	1		T121	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T108	2		T118	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T47	1		T49	1		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T47	1		T48	1		T117	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T120	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T47	1		T48	1		T49	2