Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	717592	1			T2	43		T4	37		T12	8
auto[1]	10602507	1			T1	1567		T2	147		T4	315
auto[2]	580018	1			T2	27		T4	25		T12	4
auto[3]	10471158	1			T1	1522		T2	178		T4	309

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14295272	1			T1	3089		T4	494		T10	8309
auto[1]	2152523	1			T2	4		T4	71		T12	16
auto[2]	2164241	1			T2	27		T4	106		T12	21
auto[3]	3759239	1			T2	364		T4	15		T12	4

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8580088

1

T1

3085

T2

395

T4

686

auto[1]

13791187

1

T1

4

T10

9

T13

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	217051	1			T4	32		T12	8		T14	8554
auto[0]	auto[0]	auto[1]	22598	1			T4	3		T14	833		T21	4
auto[0]	auto[0]	auto[2]	22617	1			T4	2		T14	805		T21	5
auto[0]	auto[0]	auto[3]	8409	1			T2	43		T13	16		T14	77
auto[0]	auto[1]	auto[0]	3305781	1			T1	1565		T4	246		T10	4227
auto[0]	auto[1]	auto[1]	343306	1			T2	1		T4	44		T12	9
auto[0]	auto[1]	auto[2]	335876	1			T2	8		T4	20		T12	2
auto[0]	auto[1]	auto[3]	78376	1			T2	138		T4	5		T12	1
auto[0]	auto[2]	auto[0]	175299	1			T14	7639		T26	7		T22	6448
auto[0]	auto[2]	auto[1]	18417	1			T14	757		T22	639		T122	195
auto[0]	auto[2]	auto[2]	23661	1			T2	1		T4	21		T12	4
auto[0]	auto[2]	auto[3]	7413	1			T2	26		T4	4		T13	12
auto[0]	auto[3]	auto[0]	3267093	1			T1	1520		T4	216		T10	4073
auto[0]	auto[3]	auto[1]	331313	1			T2	3		T4	24		T12	7
auto[0]	auto[3]	auto[2]	342793	1			T2	18		T4	63		T12	15
auto[0]	auto[3]	auto[3]	80085	1			T2	157		T4	6		T12	3
auto[1]	auto[0]	auto[0]	14973	1			T14	10		T22	11		T92	371
auto[1]	auto[0]	auto[1]	66023	1			T22	2		T92	1710		T94	1378
auto[1]	auto[0]	auto[2]	66618	1			T92	1737		T127	1		T94	1379
auto[1]	auto[0]	auto[3]	299303	1			T14	1		T22	1		T92	7771
auto[1]	auto[1]	auto[0]	3652623	1			T1	2		T10	3		T27	2
auto[1]	auto[1]	auto[1]	676310	1			T27	1		T34	5503		T29	9
auto[1]	auto[1]	auto[2]	656812	1			T34	6453		T29	3		T28	2
auto[1]	auto[1]	auto[3]	1553423	1			T34	583		T29	1		T35	452
auto[1]	auto[2]	auto[0]	11755	1			T14	4		T22	5		T92	377
auto[1]	auto[2]	auto[1]	52475	1			T22	1		T92	1506		T57	1
auto[1]	auto[2]	auto[2]	52734	1			T14	3		T22	3		T50	1
auto[1]	auto[2]	auto[3]	238264	1			T7	1		T92	5086		T94	6019
auto[1]	auto[3]	auto[0]	3650697	1			T1	2		T10	6		T27	3
auto[1]	auto[3]	auto[1]	642081	1			T27	1		T34	6374		T29	4
auto[1]	auto[3]	auto[2]	663130	1			T13	1		T34	5747		T29	2
auto[1]	auto[3]	auto[3]	1493966	1			T34	552		T35	405		T36	1