Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	300310447	188844	0	0
ctrl_regwen_rd_A	300310447	3772	0	0
exec_rd_A	300310447	3529	0	0
exec_regwen_rd_A	300310447	3695	0	0
readback_rd_A	300310447	2551	0	0
readback_regwen_rd_A	300310447	2466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300310447	188844	0	0
T6	29582	0	0	0
T7	156112	0	0	0
T21	209053	3814	0	0
T22	646232	0	0	0
T23	0	4302	0	0
T26	91831	2519	0	0
T37	258134	0	0	0
T39	0	6392	0	0
T43	0	7184	0	0
T44	0	8744	0	0
T46	0	2732	0	0
T50	105353	0	0	0
T52	10535	0	0	0
T58	0	1191	0	0
T59	0	2177	0	0
T60	0	4870	0	0
T61	89191	0	0	0
T62	22023	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300310447	3772	0	0
T6	29582	0	0	0
T7	156112	0	0	0
T21	209053	198	0	0
T22	646232	0	0	0
T26	91831	189	0	0
T37	258134	0	0	0
T46	0	319	0	0
T50	105353	0	0	0
T52	10535	0	0	0
T61	89191	0	0	0
T62	22023	0	0	0
T88	0	21	0	0
T100	0	165	0	0
T101	0	413	0	0
T102	0	39	0	0
T103	0	418	0	0
T104	0	750	0	0
T105	0	122	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300310447	3529	0	0
T6	29582	0	0	0
T7	156112	0	0	0
T21	209053	286	0	0
T22	646232	0	0	0
T26	91831	185	0	0
T37	258134	0	0	0
T46	0	288	0	0
T50	105353	0	0	0
T52	10535	0	0	0
T61	89191	0	0	0
T62	22023	0	0	0
T88	0	4	0	0
T100	0	136	0	0
T101	0	322	0	0
T102	0	35	0	0
T103	0	370	0	0
T104	0	614	0	0
T105	0	110	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300310447	3695	0	0
T6	29582	0	0	0
T7	156112	0	0	0
T21	209053	246	0	0
T22	646232	0	0	0
T26	91831	206	0	0
T37	258134	0	0	0
T46	0	224	0	0
T50	105353	0	0	0
T52	10535	0	0	0
T61	89191	0	0	0
T62	22023	0	0	0
T88	0	11	0	0
T100	0	174	0	0
T101	0	336	0	0
T102	0	68	0	0
T103	0	387	0	0
T104	0	645	0	0
T105	0	145	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300310447	2551	0	0
T6	29582	0	0	0
T7	156112	0	0	0
T21	209053	213	0	0
T22	646232	0	0	0
T26	91831	196	0	0
T37	258134	0	0	0
T46	0	244	0	0
T50	105353	0	0	0
T52	10535	0	0	0
T61	89191	0	0	0
T62	22023	0	0	0
T100	0	176	0	0
T101	0	437	0	0
T102	0	54	0	0
T103	0	331	0	0
T104	0	612	0	0
T105	0	123	0	0
T106	0	52	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300310447	2466	0	0
T6	29582	0	0	0
T7	156112	0	0	0
T21	209053	270	0	0
T22	646232	0	0	0
T26	91831	218	0	0
T37	258134	0	0	0
T46	0	217	0	0
T50	105353	0	0	0
T52	10535	0	0	0
T61	89191	0	0	0
T62	22023	0	0	0
T100	0	179	0	0
T101	0	365	0	0
T102	0	31	0	0
T103	0	384	0	0
T104	0	566	0	0
T105	0	98	0	0
T106	0	20	0	0