| T799 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3007996337 |
|
|
Aug 05 05:50:02 PM PDT 24 |
Aug 05 05:50:07 PM PDT 24 |
332633933 ps |
| T800 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3166091868 |
|
|
Aug 05 05:50:22 PM PDT 24 |
Aug 05 05:57:43 PM PDT 24 |
65998169741 ps |
| T801 |
/workspace/coverage/default/27.sram_ctrl_smoke.3885042602 |
|
|
Aug 05 05:51:06 PM PDT 24 |
Aug 05 05:51:45 PM PDT 24 |
5691237387 ps |
| T802 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.22646564 |
|
|
Aug 05 05:53:10 PM PDT 24 |
Aug 05 05:54:11 PM PDT 24 |
420623582 ps |
| T803 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.671416451 |
|
|
Aug 05 05:50:35 PM PDT 24 |
Aug 05 05:53:41 PM PDT 24 |
7871780151 ps |
| T804 |
/workspace/coverage/default/20.sram_ctrl_executable.3782526984 |
|
|
Aug 05 05:50:38 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
8095030961 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.4253515855 |
|
|
Aug 05 05:50:27 PM PDT 24 |
Aug 05 05:56:48 PM PDT 24 |
11883751187 ps |
| T806 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1350654847 |
|
|
Aug 05 05:53:31 PM PDT 24 |
Aug 05 05:53:34 PM PDT 24 |
123305663 ps |
| T807 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3648819093 |
|
|
Aug 05 05:50:56 PM PDT 24 |
Aug 05 05:51:00 PM PDT 24 |
426582861 ps |
| T808 |
/workspace/coverage/default/2.sram_ctrl_stress_all.483685214 |
|
|
Aug 05 05:49:51 PM PDT 24 |
Aug 05 06:43:13 PM PDT 24 |
10366870534 ps |
| T809 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4111720950 |
|
|
Aug 05 05:53:06 PM PDT 24 |
Aug 05 06:04:33 PM PDT 24 |
3267311670 ps |
| T810 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2355123182 |
|
|
Aug 05 05:51:24 PM PDT 24 |
Aug 05 06:01:00 PM PDT 24 |
21837943931 ps |
| T811 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3737877092 |
|
|
Aug 05 05:50:45 PM PDT 24 |
Aug 05 05:51:28 PM PDT 24 |
91626493 ps |
| T812 |
/workspace/coverage/default/10.sram_ctrl_executable.650187130 |
|
|
Aug 05 05:50:14 PM PDT 24 |
Aug 05 05:58:27 PM PDT 24 |
10351553949 ps |
| T813 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1285033166 |
|
|
Aug 05 05:50:48 PM PDT 24 |
Aug 05 05:50:51 PM PDT 24 |
99254278 ps |
| T814 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.502546517 |
|
|
Aug 05 05:52:03 PM PDT 24 |
Aug 05 05:52:09 PM PDT 24 |
310390236 ps |
| T815 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2575286849 |
|
|
Aug 05 05:52:55 PM PDT 24 |
Aug 05 05:52:56 PM PDT 24 |
16002873 ps |
| T816 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3375402951 |
|
|
Aug 05 05:49:52 PM PDT 24 |
Aug 05 05:52:02 PM PDT 24 |
535208150 ps |
| T817 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3070457059 |
|
|
Aug 05 05:52:05 PM PDT 24 |
Aug 05 05:52:09 PM PDT 24 |
176051469 ps |
| T818 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.959372469 |
|
|
Aug 05 05:50:06 PM PDT 24 |
Aug 05 06:03:01 PM PDT 24 |
11198651367 ps |
| T819 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3353847861 |
|
|
Aug 05 05:50:36 PM PDT 24 |
Aug 05 05:50:42 PM PDT 24 |
662817650 ps |
| T820 |
/workspace/coverage/default/23.sram_ctrl_bijection.220454154 |
|
|
Aug 05 05:50:55 PM PDT 24 |
Aug 05 05:51:29 PM PDT 24 |
4134188123 ps |
| T821 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2120965192 |
|
|
Aug 05 05:50:00 PM PDT 24 |
Aug 05 05:50:01 PM PDT 24 |
31840412 ps |
| T822 |
/workspace/coverage/default/6.sram_ctrl_executable.3497268331 |
|
|
Aug 05 05:49:57 PM PDT 24 |
Aug 05 06:09:58 PM PDT 24 |
10892714872 ps |
| T823 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1697006461 |
|
|
Aug 05 05:52:28 PM PDT 24 |
Aug 05 05:55:41 PM PDT 24 |
2208202412 ps |
| T824 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1549396877 |
|
|
Aug 05 05:50:51 PM PDT 24 |
Aug 05 05:55:53 PM PDT 24 |
11819514609 ps |
| T825 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1281381882 |
|
|
Aug 05 05:50:08 PM PDT 24 |
Aug 05 05:50:09 PM PDT 24 |
42676825 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1461357315 |
|
|
Aug 05 05:50:02 PM PDT 24 |
Aug 05 06:21:22 PM PDT 24 |
141520821016 ps |
| T827 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.3226431667 |
|
|
Aug 05 05:50:46 PM PDT 24 |
Aug 05 05:50:51 PM PDT 24 |
882920622 ps |
| T828 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.797821091 |
|
|
Aug 05 05:50:58 PM PDT 24 |
Aug 05 06:09:06 PM PDT 24 |
2917536594 ps |
| T829 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3719340137 |
|
|
Aug 05 05:50:11 PM PDT 24 |
Aug 05 05:50:18 PM PDT 24 |
1378686382 ps |
| T830 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3561501654 |
|
|
Aug 05 05:51:12 PM PDT 24 |
Aug 05 05:51:15 PM PDT 24 |
89313149 ps |
| T831 |
/workspace/coverage/default/29.sram_ctrl_bijection.2632330707 |
|
|
Aug 05 05:51:13 PM PDT 24 |
Aug 05 05:51:45 PM PDT 24 |
496618626 ps |
| T832 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1150249775 |
|
|
Aug 05 05:51:36 PM PDT 24 |
Aug 05 06:09:33 PM PDT 24 |
9922780450 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.1065992752 |
|
|
Aug 05 05:49:53 PM PDT 24 |
Aug 05 05:50:01 PM PDT 24 |
630987038 ps |
| T834 |
/workspace/coverage/default/36.sram_ctrl_regwen.2772686636 |
|
|
Aug 05 05:51:52 PM PDT 24 |
Aug 05 06:10:40 PM PDT 24 |
16745746073 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.4170817468 |
|
|
Aug 05 05:51:16 PM PDT 24 |
Aug 05 05:51:17 PM PDT 24 |
74725162 ps |
| T836 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.3335400093 |
|
|
Aug 05 05:51:14 PM PDT 24 |
Aug 05 05:51:24 PM PDT 24 |
2464791941 ps |
| T837 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3833292124 |
|
|
Aug 05 05:51:18 PM PDT 24 |
Aug 05 05:51:19 PM PDT 24 |
35901528 ps |
| T838 |
/workspace/coverage/default/11.sram_ctrl_executable.3808204277 |
|
|
Aug 05 05:50:33 PM PDT 24 |
Aug 05 05:54:23 PM PDT 24 |
1142894432 ps |
| T839 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2998086213 |
|
|
Aug 05 05:50:27 PM PDT 24 |
Aug 05 05:50:28 PM PDT 24 |
86641159 ps |
| T840 |
/workspace/coverage/default/36.sram_ctrl_executable.2569086592 |
|
|
Aug 05 05:51:49 PM PDT 24 |
Aug 05 06:02:40 PM PDT 24 |
51561533808 ps |
| T841 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1629562047 |
|
|
Aug 05 05:51:59 PM PDT 24 |
Aug 05 05:51:59 PM PDT 24 |
76297066 ps |
| T842 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2399270376 |
|
|
Aug 05 05:50:36 PM PDT 24 |
Aug 05 05:51:43 PM PDT 24 |
232032794 ps |
| T843 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.804834615 |
|
|
Aug 05 05:50:29 PM PDT 24 |
Aug 05 05:59:33 PM PDT 24 |
4872152452 ps |
| T844 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1376215722 |
|
|
Aug 05 05:52:26 PM PDT 24 |
Aug 05 05:52:31 PM PDT 24 |
393483177 ps |
| T845 |
/workspace/coverage/default/46.sram_ctrl_regwen.2022475463 |
|
|
Aug 05 05:53:06 PM PDT 24 |
Aug 05 05:55:00 PM PDT 24 |
4028495820 ps |
| T846 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.435811392 |
|
|
Aug 05 05:50:40 PM PDT 24 |
Aug 05 05:52:04 PM PDT 24 |
253358906 ps |
| T847 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2726110204 |
|
|
Aug 05 05:50:48 PM PDT 24 |
Aug 05 05:54:30 PM PDT 24 |
2736037165 ps |
| T848 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2939134378 |
|
|
Aug 05 05:50:51 PM PDT 24 |
Aug 05 05:58:19 PM PDT 24 |
40196641708 ps |
| T849 |
/workspace/coverage/default/39.sram_ctrl_executable.1864681120 |
|
|
Aug 05 05:52:14 PM PDT 24 |
Aug 05 06:10:55 PM PDT 24 |
64274515223 ps |
| T850 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1907851024 |
|
|
Aug 05 05:52:13 PM PDT 24 |
Aug 05 05:52:14 PM PDT 24 |
34949861 ps |
| T851 |
/workspace/coverage/default/37.sram_ctrl_stress_all.89008870 |
|
|
Aug 05 05:52:04 PM PDT 24 |
Aug 05 06:44:53 PM PDT 24 |
33326476977 ps |
| T852 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1835631888 |
|
|
Aug 05 05:51:54 PM PDT 24 |
Aug 05 05:51:57 PM PDT 24 |
186558979 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_stress_all.730410278 |
|
|
Aug 05 05:53:23 PM PDT 24 |
Aug 05 06:28:56 PM PDT 24 |
73706801289 ps |
| T854 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1929105274 |
|
|
Aug 05 05:51:08 PM PDT 24 |
Aug 05 05:51:09 PM PDT 24 |
36097858 ps |
| T855 |
/workspace/coverage/default/43.sram_ctrl_smoke.2236066163 |
|
|
Aug 05 05:52:37 PM PDT 24 |
Aug 05 05:52:39 PM PDT 24 |
113726975 ps |
| T856 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2791023506 |
|
|
Aug 05 05:50:13 PM PDT 24 |
Aug 05 05:50:19 PM PDT 24 |
2704864432 ps |
| T857 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1423948063 |
|
|
Aug 05 05:50:04 PM PDT 24 |
Aug 05 05:58:36 PM PDT 24 |
2149682515 ps |
| T858 |
/workspace/coverage/default/27.sram_ctrl_partial_access.296023551 |
|
|
Aug 05 05:51:03 PM PDT 24 |
Aug 05 05:51:44 PM PDT 24 |
149740999 ps |
| T859 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.606004555 |
|
|
Aug 05 05:52:51 PM PDT 24 |
Aug 05 05:52:57 PM PDT 24 |
367848522 ps |
| T860 |
/workspace/coverage/default/21.sram_ctrl_executable.173251224 |
|
|
Aug 05 05:50:47 PM PDT 24 |
Aug 05 06:09:01 PM PDT 24 |
17778815800 ps |
| T861 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1430918811 |
|
|
Aug 05 05:50:32 PM PDT 24 |
Aug 05 05:52:58 PM PDT 24 |
2970623259 ps |
| T862 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2492307828 |
|
|
Aug 05 05:50:31 PM PDT 24 |
Aug 05 06:07:48 PM PDT 24 |
11281656768 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3209361689 |
|
|
Aug 05 05:50:50 PM PDT 24 |
Aug 05 05:50:53 PM PDT 24 |
266529157 ps |
| T864 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3484704458 |
|
|
Aug 05 05:50:44 PM PDT 24 |
Aug 05 05:51:06 PM PDT 24 |
610934078 ps |
| T865 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.3236614852 |
|
|
Aug 05 05:51:18 PM PDT 24 |
Aug 05 05:51:20 PM PDT 24 |
470148211 ps |
| T105 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1875601154 |
|
|
Aug 05 05:51:26 PM PDT 24 |
Aug 05 05:52:57 PM PDT 24 |
3747701020 ps |
| T866 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.253079527 |
|
|
Aug 05 05:50:02 PM PDT 24 |
Aug 05 05:53:59 PM PDT 24 |
3096782160 ps |
| T867 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3300284280 |
|
|
Aug 05 05:52:45 PM PDT 24 |
Aug 05 05:58:24 PM PDT 24 |
6793834967 ps |
| T868 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1554732237 |
|
|
Aug 05 05:51:19 PM PDT 24 |
Aug 05 05:56:53 PM PDT 24 |
4409468256 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2658285024 |
|
|
Aug 05 05:53:19 PM PDT 24 |
Aug 05 05:53:20 PM PDT 24 |
31965170 ps |
| T870 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.3673723237 |
|
|
Aug 05 05:51:19 PM PDT 24 |
Aug 05 05:51:25 PM PDT 24 |
226184997 ps |
| T871 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2844394259 |
|
|
Aug 05 05:51:24 PM PDT 24 |
Aug 05 05:53:00 PM PDT 24 |
622327885 ps |
| T79 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1927878640 |
|
|
Aug 05 05:53:22 PM PDT 24 |
Aug 05 05:53:25 PM PDT 24 |
414051018 ps |
| T872 |
/workspace/coverage/default/37.sram_ctrl_smoke.1970758031 |
|
|
Aug 05 05:51:53 PM PDT 24 |
Aug 05 05:52:10 PM PDT 24 |
2561231081 ps |
| T873 |
/workspace/coverage/default/36.sram_ctrl_alert_test.4234084590 |
|
|
Aug 05 05:51:50 PM PDT 24 |
Aug 05 05:51:51 PM PDT 24 |
118774742 ps |
| T874 |
/workspace/coverage/default/15.sram_ctrl_regwen.2427965508 |
|
|
Aug 05 05:50:36 PM PDT 24 |
Aug 05 06:09:43 PM PDT 24 |
3489141652 ps |
| T875 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3564557348 |
|
|
Aug 05 05:50:44 PM PDT 24 |
Aug 05 05:56:34 PM PDT 24 |
25403590291 ps |
| T876 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.983596868 |
|
|
Aug 05 05:53:27 PM PDT 24 |
Aug 05 05:54:22 PM PDT 24 |
203835187 ps |
| T877 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.230382451 |
|
|
Aug 05 05:51:19 PM PDT 24 |
Aug 05 05:57:07 PM PDT 24 |
1101229121 ps |
| T878 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.560859106 |
|
|
Aug 05 05:50:35 PM PDT 24 |
Aug 05 05:58:55 PM PDT 24 |
85943503293 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_bijection.3926981807 |
|
|
Aug 05 05:51:18 PM PDT 24 |
Aug 05 05:51:55 PM PDT 24 |
1684690368 ps |
| T880 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1186828805 |
|
|
Aug 05 05:51:32 PM PDT 24 |
Aug 05 05:51:43 PM PDT 24 |
679953657 ps |
| T881 |
/workspace/coverage/default/44.sram_ctrl_alert_test.886019788 |
|
|
Aug 05 05:52:50 PM PDT 24 |
Aug 05 05:52:51 PM PDT 24 |
39485030 ps |
| T882 |
/workspace/coverage/default/19.sram_ctrl_alert_test.926765000 |
|
|
Aug 05 05:50:45 PM PDT 24 |
Aug 05 05:50:46 PM PDT 24 |
44078211 ps |
| T883 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1391099562 |
|
|
Aug 05 05:53:28 PM PDT 24 |
Aug 05 06:16:03 PM PDT 24 |
70044823966 ps |
| T884 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3788974109 |
|
|
Aug 05 05:50:47 PM PDT 24 |
Aug 05 06:17:01 PM PDT 24 |
102821281371 ps |
| T885 |
/workspace/coverage/default/35.sram_ctrl_smoke.104895944 |
|
|
Aug 05 05:51:39 PM PDT 24 |
Aug 05 05:51:48 PM PDT 24 |
294516006 ps |
| T886 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1898185916 |
|
|
Aug 05 05:50:52 PM PDT 24 |
Aug 05 05:50:53 PM PDT 24 |
67666078 ps |
| T887 |
/workspace/coverage/default/13.sram_ctrl_regwen.1682520388 |
|
|
Aug 05 05:50:41 PM PDT 24 |
Aug 05 05:56:44 PM PDT 24 |
1683395051 ps |
| T888 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2554397756 |
|
|
Aug 05 05:51:08 PM PDT 24 |
Aug 05 05:51:16 PM PDT 24 |
1300284113 ps |
| T889 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2803653377 |
|
|
Aug 05 05:50:24 PM PDT 24 |
Aug 05 05:50:43 PM PDT 24 |
3118580803 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1020045505 |
|
|
Aug 05 05:51:23 PM PDT 24 |
Aug 05 05:51:24 PM PDT 24 |
51472868 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_regwen.1654113320 |
|
|
Aug 05 05:50:46 PM PDT 24 |
Aug 05 05:56:16 PM PDT 24 |
1647762477 ps |
| T892 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1832362658 |
|
|
Aug 05 05:50:43 PM PDT 24 |
Aug 05 05:50:45 PM PDT 24 |
84625669 ps |
| T893 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.729910070 |
|
|
Aug 05 05:50:10 PM PDT 24 |
Aug 05 06:09:47 PM PDT 24 |
8073955994 ps |
| T894 |
/workspace/coverage/default/2.sram_ctrl_smoke.4012771159 |
|
|
Aug 05 05:50:11 PM PDT 24 |
Aug 05 05:50:21 PM PDT 24 |
465134731 ps |
| T895 |
/workspace/coverage/default/18.sram_ctrl_regwen.3073681746 |
|
|
Aug 05 05:50:43 PM PDT 24 |
Aug 05 06:08:39 PM PDT 24 |
10530050952 ps |
| T896 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1862387264 |
|
|
Aug 05 05:50:10 PM PDT 24 |
Aug 05 06:00:32 PM PDT 24 |
6567399574 ps |
| T897 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1718096432 |
|
|
Aug 05 05:50:11 PM PDT 24 |
Aug 05 05:50:12 PM PDT 24 |
117257531 ps |
| T898 |
/workspace/coverage/default/24.sram_ctrl_regwen.1798934848 |
|
|
Aug 05 05:50:57 PM PDT 24 |
Aug 05 05:58:18 PM PDT 24 |
29080824047 ps |
| T899 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.828489455 |
|
|
Aug 05 05:51:49 PM PDT 24 |
Aug 05 05:51:56 PM PDT 24 |
2169230369 ps |
| T900 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2025833008 |
|
|
Aug 05 05:50:33 PM PDT 24 |
Aug 05 05:55:07 PM PDT 24 |
24026447966 ps |
| T901 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2247403725 |
|
|
Aug 05 05:50:07 PM PDT 24 |
Aug 05 05:50:14 PM PDT 24 |
224283174 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.497031609 |
|
|
Aug 05 05:51:22 PM PDT 24 |
Aug 05 05:51:26 PM PDT 24 |
455705204 ps |
| T903 |
/workspace/coverage/default/47.sram_ctrl_executable.563424071 |
|
|
Aug 05 05:53:13 PM PDT 24 |
Aug 05 06:02:32 PM PDT 24 |
7893213368 ps |
| T904 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.54077795 |
|
|
Aug 05 05:51:35 PM PDT 24 |
Aug 05 05:58:33 PM PDT 24 |
18434965953 ps |
| T905 |
/workspace/coverage/default/5.sram_ctrl_partial_access.862334138 |
|
|
Aug 05 05:50:02 PM PDT 24 |
Aug 05 05:50:19 PM PDT 24 |
1291684991 ps |
| T906 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.1481891247 |
|
|
Aug 05 05:50:08 PM PDT 24 |
Aug 05 05:50:08 PM PDT 24 |
94224064 ps |
| T907 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1740705911 |
|
|
Aug 05 05:53:30 PM PDT 24 |
Aug 05 05:53:31 PM PDT 24 |
84071344 ps |
| T908 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.224101532 |
|
|
Aug 05 05:50:11 PM PDT 24 |
Aug 05 06:12:36 PM PDT 24 |
13628753169 ps |
| T909 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4016502756 |
|
|
Aug 05 05:50:19 PM PDT 24 |
Aug 05 05:58:06 PM PDT 24 |
19869238617 ps |
| T910 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3927816174 |
|
|
Aug 05 05:52:52 PM PDT 24 |
Aug 05 06:03:23 PM PDT 24 |
18038086592 ps |
| T911 |
/workspace/coverage/default/33.sram_ctrl_executable.3313041663 |
|
|
Aug 05 05:51:32 PM PDT 24 |
Aug 05 06:15:06 PM PDT 24 |
50532178401 ps |
| T912 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1997626207 |
|
|
Aug 05 05:49:54 PM PDT 24 |
Aug 05 05:52:54 PM PDT 24 |
4180383444 ps |
| T913 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.923736774 |
|
|
Aug 05 05:49:47 PM PDT 24 |
Aug 05 05:49:51 PM PDT 24 |
487247316 ps |
| T914 |
/workspace/coverage/default/42.sram_ctrl_smoke.3619225027 |
|
|
Aug 05 05:52:28 PM PDT 24 |
Aug 05 05:52:44 PM PDT 24 |
1902217767 ps |
| T915 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3403165669 |
|
|
Aug 05 05:52:44 PM PDT 24 |
Aug 05 05:52:56 PM PDT 24 |
2985030116 ps |
| T916 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4272807767 |
|
|
Aug 05 05:49:42 PM PDT 24 |
Aug 05 05:58:30 PM PDT 24 |
6273704783 ps |
| T33 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1892023806 |
|
|
Aug 05 05:50:14 PM PDT 24 |
Aug 05 05:50:16 PM PDT 24 |
574244392 ps |
| T917 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3255457215 |
|
|
Aug 05 05:49:59 PM PDT 24 |
Aug 05 05:54:59 PM PDT 24 |
11137215859 ps |
| T918 |
/workspace/coverage/default/23.sram_ctrl_stress_all.297747365 |
|
|
Aug 05 05:50:55 PM PDT 24 |
Aug 05 06:08:28 PM PDT 24 |
71347341897 ps |
| T919 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1352865747 |
|
|
Aug 05 05:49:47 PM PDT 24 |
Aug 05 05:49:58 PM PDT 24 |
2834978394 ps |
| T920 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1797247241 |
|
|
Aug 05 05:51:27 PM PDT 24 |
Aug 05 05:51:29 PM PDT 24 |
63085175 ps |
| T921 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1567226168 |
|
|
Aug 05 05:50:33 PM PDT 24 |
Aug 05 05:50:33 PM PDT 24 |
51510056 ps |
| T922 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3793125642 |
|
|
Aug 05 05:50:02 PM PDT 24 |
Aug 05 05:53:45 PM PDT 24 |
2304571376 ps |
| T923 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.807271205 |
|
|
Aug 05 05:52:21 PM PDT 24 |
Aug 05 05:52:38 PM PDT 24 |
155763082 ps |
| T924 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3199964925 |
|
|
Aug 05 05:50:25 PM PDT 24 |
Aug 05 05:54:38 PM PDT 24 |
17882375396 ps |
| T925 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1176014980 |
|
|
Aug 05 05:50:43 PM PDT 24 |
Aug 05 05:50:51 PM PDT 24 |
1712042071 ps |
| T926 |
/workspace/coverage/default/36.sram_ctrl_stress_all.4246577507 |
|
|
Aug 05 05:51:49 PM PDT 24 |
Aug 05 05:58:54 PM PDT 24 |
43635489010 ps |
| T927 |
/workspace/coverage/default/6.sram_ctrl_smoke.2356217147 |
|
|
Aug 05 05:49:57 PM PDT 24 |
Aug 05 05:50:15 PM PDT 24 |
570603646 ps |
| T928 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1449901476 |
|
|
Aug 05 05:50:04 PM PDT 24 |
Aug 05 05:51:25 PM PDT 24 |
262802504 ps |
| T929 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1886556648 |
|
|
Aug 05 05:50:07 PM PDT 24 |
Aug 05 05:50:18 PM PDT 24 |
178252912 ps |
| T930 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1468799320 |
|
|
Aug 05 05:50:40 PM PDT 24 |
Aug 05 05:50:40 PM PDT 24 |
31394771 ps |
| T931 |
/workspace/coverage/default/17.sram_ctrl_smoke.3732350933 |
|
|
Aug 05 05:50:31 PM PDT 24 |
Aug 05 05:50:35 PM PDT 24 |
85348778 ps |
| T932 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3583591166 |
|
|
Aug 05 05:51:20 PM PDT 24 |
Aug 05 05:59:37 PM PDT 24 |
18662994380 ps |
| T933 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3768195576 |
|
|
Aug 05 05:50:02 PM PDT 24 |
Aug 05 05:50:07 PM PDT 24 |
440185339 ps |
| T934 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2135011480 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:02 PM PDT 24 |
269696181 ps |
| T54 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2075506980 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
19140157 ps |
| T55 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3915902730 |
|
|
Aug 05 06:06:58 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
47691257 ps |
| T935 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1887183195 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
35312671 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4214650887 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
251298769 ps |
| T64 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.300004708 |
|
|
Aug 05 06:07:05 PM PDT 24 |
Aug 05 06:07:06 PM PDT 24 |
81580362 ps |
| T99 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1266289374 |
|
|
Aug 05 06:06:44 PM PDT 24 |
Aug 05 06:06:45 PM PDT 24 |
47475367 ps |
| T87 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.607094710 |
|
|
Aug 05 06:06:58 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
61980425 ps |
| T88 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3752113606 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
85203334 ps |
| T47 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3496232970 |
|
|
Aug 05 06:07:04 PM PDT 24 |
Aug 05 06:07:06 PM PDT 24 |
559609272 ps |
| T65 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.554072097 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
441382372 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.299215942 |
|
|
Aug 05 06:06:52 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
111457719 ps |
| T67 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1244814393 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
221867975 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3680711985 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
23356746 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2211553813 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
41699013 ps |
| T106 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2012123309 |
|
|
Aug 05 06:06:47 PM PDT 24 |
Aug 05 06:06:52 PM PDT 24 |
129002258 ps |
| T48 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.433458497 |
|
|
Aug 05 06:06:58 PM PDT 24 |
Aug 05 06:07:00 PM PDT 24 |
359816524 ps |
| T49 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2484313960 |
|
|
Aug 05 06:06:57 PM PDT 24 |
Aug 05 06:06:59 PM PDT 24 |
338925037 ps |
| T117 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1414597673 |
|
|
Aug 05 06:06:45 PM PDT 24 |
Aug 05 06:06:47 PM PDT 24 |
449305677 ps |
| T70 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1769789704 |
|
|
Aug 05 06:06:46 PM PDT 24 |
Aug 05 06:06:47 PM PDT 24 |
13658408 ps |
| T936 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1116993373 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
33417864 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3151272259 |
|
|
Aug 05 06:06:49 PM PDT 24 |
Aug 05 06:06:51 PM PDT 24 |
669023615 ps |
| T114 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1140888101 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
307981566 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.230232729 |
|
|
Aug 05 06:06:48 PM PDT 24 |
Aug 05 06:06:51 PM PDT 24 |
570243994 ps |
| T89 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.125851867 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
49273494 ps |
| T937 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2244564586 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
99500825 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.872415008 |
|
|
Aug 05 06:06:50 PM PDT 24 |
Aug 05 06:06:51 PM PDT 24 |
15409257 ps |
| T71 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2213937720 |
|
|
Aug 05 06:06:55 PM PDT 24 |
Aug 05 06:06:56 PM PDT 24 |
58442796 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2654468231 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:56 PM PDT 24 |
683613886 ps |
| T120 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3882146738 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:05 PM PDT 24 |
883959438 ps |
| T938 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.917571353 |
|
|
Aug 05 06:06:47 PM PDT 24 |
Aug 05 06:06:48 PM PDT 24 |
35512333 ps |
| T939 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3999833051 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:56 PM PDT 24 |
319257619 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2231388462 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
67573217 ps |
| T73 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.766601148 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:02 PM PDT 24 |
2545444004 ps |
| T941 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.718024563 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:00 PM PDT 24 |
49567350 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2975550107 |
|
|
Aug 05 06:06:55 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
121215414 ps |
| T943 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3514994902 |
|
|
Aug 05 06:07:01 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
15008640 ps |
| T74 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.121283525 |
|
|
Aug 05 06:07:01 PM PDT 24 |
Aug 05 06:07:03 PM PDT 24 |
790631665 ps |
| T944 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1251473237 |
|
|
Aug 05 06:06:51 PM PDT 24 |
Aug 05 06:06:52 PM PDT 24 |
19950154 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3743318162 |
|
|
Aug 05 06:06:47 PM PDT 24 |
Aug 05 06:06:48 PM PDT 24 |
37740655 ps |
| T121 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2498226330 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
265266794 ps |
| T946 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1006328981 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
46140576 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2558008791 |
|
|
Aug 05 06:06:55 PM PDT 24 |
Aug 05 06:06:59 PM PDT 24 |
133566720 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3747022872 |
|
|
Aug 05 06:06:58 PM PDT 24 |
Aug 05 06:07:00 PM PDT 24 |
429160614 ps |
| T948 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.887488225 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:03 PM PDT 24 |
539023460 ps |
| T949 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.314129836 |
|
|
Aug 05 06:07:03 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
19107156 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1122889878 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:05 PM PDT 24 |
81583794 ps |
| T80 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.415622776 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
20623181 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2762409426 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:03 PM PDT 24 |
44776287 ps |
| T118 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3633820644 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
76885227 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.335386524 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
31039443 ps |
| T81 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.594520142 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:02 PM PDT 24 |
202519701 ps |
| T86 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.595748420 |
|
|
Aug 05 06:06:57 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
20559641 ps |
| T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1858162153 |
|
|
Aug 05 06:06:52 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
235230190 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3697461309 |
|
|
Aug 05 06:06:52 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
104234617 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1796728268 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:05 PM PDT 24 |
412652877 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2278992702 |
|
|
Aug 05 06:06:52 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
36323842 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4110681674 |
|
|
Aug 05 06:06:45 PM PDT 24 |
Aug 05 06:06:46 PM PDT 24 |
90906766 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3123777790 |
|
|
Aug 05 06:06:47 PM PDT 24 |
Aug 05 06:06:47 PM PDT 24 |
25649324 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4051272087 |
|
|
Aug 05 06:06:49 PM PDT 24 |
Aug 05 06:06:50 PM PDT 24 |
14152991 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3917665932 |
|
|
Aug 05 06:06:55 PM PDT 24 |
Aug 05 06:06:59 PM PDT 24 |
1390027443 ps |
| T115 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.232189080 |
|
|
Aug 05 06:06:57 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
142046172 ps |
| T84 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3639339960 |
|
|
Aug 05 06:06:51 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
854256873 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1917368051 |
|
|
Aug 05 06:06:47 PM PDT 24 |
Aug 05 06:06:50 PM PDT 24 |
549004361 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3322384277 |
|
|
Aug 05 06:06:57 PM PDT 24 |
Aug 05 06:06:58 PM PDT 24 |
13145373 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1068152336 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
12760786 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3598017950 |
|
|
Aug 05 06:06:51 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
111427383 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.334563326 |
|
|
Aug 05 06:06:50 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
285460859 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2913182561 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
24808731 ps |
| T119 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1601707823 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
465417928 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.277808941 |
|
|
Aug 05 06:07:05 PM PDT 24 |
Aug 05 06:07:08 PM PDT 24 |
96997607 ps |
| T965 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3782165106 |
|
|
Aug 05 06:07:03 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
89650736 ps |
| T966 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1989076874 |
|
|
Aug 05 06:06:55 PM PDT 24 |
Aug 05 06:06:59 PM PDT 24 |
114070748 ps |
| T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2123722838 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
36443635 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4150063210 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
51327162 ps |
| T969 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3762246915 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
22619234 ps |
| T970 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3918428993 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:56 PM PDT 24 |
619080064 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.934414784 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
203766914 ps |
| T972 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.981643320 |
|
|
Aug 05 06:06:49 PM PDT 24 |
Aug 05 06:06:51 PM PDT 24 |
74277505 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1156691602 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
376325772 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.322479945 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:56 PM PDT 24 |
337125685 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1161546152 |
|
|
Aug 05 06:06:51 PM PDT 24 |
Aug 05 06:06:52 PM PDT 24 |
53271496 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1036016312 |
|
|
Aug 05 06:06:52 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
229277456 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1472432187 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:02 PM PDT 24 |
769132559 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3567078425 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:03 PM PDT 24 |
45212769 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1830954139 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:56 PM PDT 24 |
81474283 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4220892462 |
|
|
Aug 05 06:06:55 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
74102516 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.345247000 |
|
|
Aug 05 06:07:00 PM PDT 24 |
Aug 05 06:07:03 PM PDT 24 |
1318808231 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.668320800 |
|
|
Aug 05 06:06:58 PM PDT 24 |
Aug 05 06:07:00 PM PDT 24 |
25126684 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1804957444 |
|
|
Aug 05 06:07:03 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
56499552 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3629704483 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
146483705 ps |
| T984 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.192730233 |
|
|
Aug 05 06:07:06 PM PDT 24 |
Aug 05 06:07:07 PM PDT 24 |
58287307 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.690973172 |
|
|
Aug 05 06:06:48 PM PDT 24 |
Aug 05 06:06:51 PM PDT 24 |
301728967 ps |
| T111 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.627386626 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
1697414613 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2637354033 |
|
|
Aug 05 06:07:05 PM PDT 24 |
Aug 05 06:07:06 PM PDT 24 |
69646187 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4279533411 |
|
|
Aug 05 06:07:03 PM PDT 24 |
Aug 05 06:07:05 PM PDT 24 |
21706474 ps |
| T988 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3073688452 |
|
|
Aug 05 06:06:52 PM PDT 24 |
Aug 05 06:06:54 PM PDT 24 |
73692717 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2978208962 |
|
|
Aug 05 06:06:46 PM PDT 24 |
Aug 05 06:06:47 PM PDT 24 |
14636982 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1606540741 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:02 PM PDT 24 |
740711675 ps |
| T991 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2293825689 |
|
|
Aug 05 06:07:06 PM PDT 24 |
Aug 05 06:07:07 PM PDT 24 |
16309707 ps |
| T992 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1230709263 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
64672056 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2419309542 |
|
|
Aug 05 06:06:53 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
259648272 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.846465533 |
|
|
Aug 05 06:06:48 PM PDT 24 |
Aug 05 06:06:49 PM PDT 24 |
48564592 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1179101835 |
|
|
Aug 05 06:06:51 PM PDT 24 |
Aug 05 06:06:53 PM PDT 24 |
26544035 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.208486492 |
|
|
Aug 05 06:06:56 PM PDT 24 |
Aug 05 06:06:57 PM PDT 24 |
26042706 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3573064210 |
|
|
Aug 05 06:07:03 PM PDT 24 |
Aug 05 06:07:04 PM PDT 24 |
114284346 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1182043039 |
|
|
Aug 05 06:06:59 PM PDT 24 |
Aug 05 06:07:01 PM PDT 24 |
130860534 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.780137724 |
|
|
Aug 05 06:06:46 PM PDT 24 |
Aug 05 06:06:47 PM PDT 24 |
68636232 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.820117466 |
|
|
Aug 05 06:06:44 PM PDT 24 |
Aug 05 06:06:48 PM PDT 24 |
2250799085 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.969733103 |
|
|
Aug 05 06:06:48 PM PDT 24 |
Aug 05 06:06:51 PM PDT 24 |
314174151 ps |
| T1002 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2116618514 |
|
|
Aug 05 06:06:54 PM PDT 24 |
Aug 05 06:06:55 PM PDT 24 |
56844353 ps |
| T1003 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1971067771 |
|
|
Aug 05 06:07:02 PM PDT 24 |
Aug 05 06:07:02 PM PDT 24 |
15387870 ps |