Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13614981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56629163

1

T1

63437

T2

95

T3

5002

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35018576	1			T1	35086		T2	823		T3	2729
values[0x0]	16250722	1			T1	16660		T2	322		T3	1280
values[0x1]	18974846	1			T1	18073		T2	763		T3	1461

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6784940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63459204

1

T1

66631

T2

877

T3

5257

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	234467	1			T1	1		T2	3		T4	88
valid_sources[0x01]	274643	1			T2	13		T4	92		T11	4
valid_sources[0x02]	327184	1			T1	31		T2	6		T4	96
valid_sources[0x03]	260403	1			T1	381		T4	178		T11	19
valid_sources[0x04]	287342	1			T1	2		T2	11		T4	141
valid_sources[0x05]	401670	1			T1	524		T4	133		T12	452
valid_sources[0x06]	270474	1			T1	37		T2	11		T4	49
valid_sources[0x07]	267071	1			T1	441		T2	2		T4	117
valid_sources[0x08]	258358	1			T1	239		T2	16		T4	138
valid_sources[0x09]	293513	1			T1	281		T2	8		T4	175
valid_sources[0x0a]	257240	1			T1	57		T2	7		T4	40
valid_sources[0x0b]	274911	1			T1	149		T2	7		T4	51
valid_sources[0x0c]	264200	1			T1	14		T2	13		T4	104
valid_sources[0x0d]	303871	1			T1	118		T2	3		T4	13
valid_sources[0x0e]	256685	1			T1	62		T2	3		T4	123
valid_sources[0x0f]	240128	1			T1	20		T2	5		T4	106
valid_sources[0x10]	266483	1			T1	265		T2	11		T4	66
valid_sources[0x11]	275702	1			T1	214		T2	8		T4	91
valid_sources[0x12]	291921	1			T1	118		T2	8		T4	59
valid_sources[0x13]	282498	1			T1	196		T2	19		T4	44
valid_sources[0x14]	279280	1			T1	53		T2	5		T4	79
valid_sources[0x15]	245443	1			T1	333		T2	8		T4	73
valid_sources[0x16]	273917	1			T1	40		T2	12		T4	110
valid_sources[0x17]	284490	1			T1	69		T2	3		T4	71
valid_sources[0x18]	315450	1			T1	33		T2	1		T4	103
valid_sources[0x19]	243523	1			T1	425		T2	4		T4	147
valid_sources[0x1a]	273534	1			T1	7		T2	6		T4	52
valid_sources[0x1b]	321023	1			T1	24		T2	19		T4	94
valid_sources[0x1c]	304589	1			T1	96		T2	16		T4	41
valid_sources[0x1d]	259853	1			T1	69		T2	5		T4	106
valid_sources[0x1e]	341890	1			T1	56		T2	3		T4	34
valid_sources[0x1f]	252181	1			T1	244		T2	12		T4	78
valid_sources[0x20]	237917	1			T1	101		T2	4		T4	54
valid_sources[0x21]	309134	1			T1	244		T2	4		T4	95
valid_sources[0x22]	243953	1			T1	147		T2	3		T4	68
valid_sources[0x23]	312700	1			T1	117		T2	1		T4	77
valid_sources[0x24]	305319	1			T1	52		T2	2		T4	92
valid_sources[0x25]	232955	1			T1	18		T2	2		T4	109
valid_sources[0x26]	288029	1			T1	85		T2	12		T4	150
valid_sources[0x27]	264215	1			T1	37		T2	2		T4	70
valid_sources[0x28]	240789	1			T1	147		T2	1		T4	80
valid_sources[0x29]	259395	1			T1	89		T2	1		T4	120
valid_sources[0x2a]	240562	1			T1	185		T4	59		T11	6
valid_sources[0x2b]	310482	1			T1	57		T2	8		T4	59
valid_sources[0x2c]	254771	1			T1	127		T2	20		T4	83
valid_sources[0x2d]	241773	1			T1	274		T2	9		T4	44
valid_sources[0x2e]	305266	1			T1	112		T2	4		T4	100
valid_sources[0x2f]	265857	1			T1	174		T2	2		T4	56
valid_sources[0x30]	262604	1			T1	139		T2	3		T4	60
valid_sources[0x31]	238809	1			T1	12		T2	4		T4	43
valid_sources[0x32]	308673	1			T1	111		T2	12		T4	59
valid_sources[0x33]	242455	1			T1	58		T2	18		T4	28
valid_sources[0x34]	258308	1			T1	270		T2	2		T4	32
valid_sources[0x35]	252156	1			T1	113		T2	6		T4	62
valid_sources[0x36]	346746	1			T1	27		T2	10		T4	91
valid_sources[0x37]	269385	1			T1	66		T2	4		T4	68
valid_sources[0x38]	248551	1			T2	6		T4	91		T12	380
valid_sources[0x39]	274413	1			T1	226		T2	6		T4	51
valid_sources[0x3a]	257006	1			T1	176		T2	7		T4	79
valid_sources[0x3b]	246802	1			T1	59		T2	5		T4	146
valid_sources[0x3c]	255801	1			T1	169		T2	12		T4	70
valid_sources[0x3d]	339532	1			T1	78		T2	11		T4	91
valid_sources[0x3e]	236620	1			T1	109		T2	18		T4	69
valid_sources[0x3f]	352286	1			T1	232		T2	10		T4	131
valid_sources[0x40]	317133	1			T1	6		T2	3		T4	84
valid_sources[0x41]	243984	1			T1	1		T2	1		T4	61
valid_sources[0x42]	309561	1			T1	13		T2	3		T4	124
valid_sources[0x43]	271432	1			T1	154		T2	10		T4	64
valid_sources[0x44]	271930	1			T1	5		T2	3		T4	60
valid_sources[0x45]	249043	1			T1	152		T2	6		T4	75
valid_sources[0x46]	280201	1			T1	64		T2	5		T4	97
valid_sources[0x47]	282867	1			T1	242		T2	19		T4	45
valid_sources[0x48]	274435	1			T1	44		T2	7		T4	49
valid_sources[0x49]	257580	1			T2	5		T4	63		T12	463
valid_sources[0x4a]	256142	1			T1	57		T2	6		T4	44
valid_sources[0x4b]	250835	1			T1	97		T2	10		T4	97
valid_sources[0x4c]	242684	1			T1	234		T2	15		T4	99
valid_sources[0x4d]	315841	1			T1	264		T2	10		T4	29
valid_sources[0x4e]	278407	1			T1	1		T2	16		T4	133
valid_sources[0x4f]	384684	1			T1	44		T2	13		T4	56
valid_sources[0x50]	277745	1			T1	470		T2	4		T4	72
valid_sources[0x51]	235952	1			T1	89		T2	2		T4	78
valid_sources[0x52]	298871	1			T1	113		T2	25		T4	55
valid_sources[0x53]	298467	1			T1	64		T2	10		T4	102
valid_sources[0x54]	254663	1			T1	63		T2	10		T4	93
valid_sources[0x55]	264464	1			T1	279		T2	2		T4	63
valid_sources[0x56]	257565	1			T1	175		T4	70		T11	3
valid_sources[0x57]	251720	1			T1	359		T2	33		T4	84
valid_sources[0x58]	281286	1			T1	131		T2	3		T4	81
valid_sources[0x59]	266739	1			T1	284		T2	1		T4	29
valid_sources[0x5a]	298985	1			T1	34		T2	1		T4	55
valid_sources[0x5b]	270395	1			T1	159		T2	3		T4	146
valid_sources[0x5c]	258301	1			T1	210		T2	15		T4	53
valid_sources[0x5d]	292223	1			T1	106		T2	3		T4	72
valid_sources[0x5e]	329496	1			T1	29		T2	5		T4	126
valid_sources[0x5f]	298532	1			T1	363		T2	33		T4	75
valid_sources[0x60]	249370	1			T1	37		T2	5		T4	65
valid_sources[0x61]	290537	1			T1	139		T2	7		T4	40
valid_sources[0x62]	272245	1			T1	57		T2	4		T4	58
valid_sources[0x63]	277171	1			T2	4		T4	89		T11	4
valid_sources[0x64]	342373	1			T1	121		T2	8		T4	54
valid_sources[0x65]	279786	1			T1	23623		T2	1		T4	55
valid_sources[0x66]	249515	1			T1	105		T2	5		T4	88
valid_sources[0x67]	266183	1			T1	80		T2	5		T4	39
valid_sources[0x68]	261885	1			T1	452		T2	7		T4	92
valid_sources[0x69]	238300	1			T1	87		T4	48		T11	3
valid_sources[0x6a]	244063	1			T1	44		T2	3		T4	114
valid_sources[0x6b]	298948	1			T2	11		T4	87		T12	377
valid_sources[0x6c]	239291	1			T1	73		T2	6		T4	156
valid_sources[0x6d]	327696	1			T1	119		T2	1		T4	110
valid_sources[0x6e]	260630	1			T1	59		T2	5		T4	83
valid_sources[0x6f]	256779	1			T1	170		T2	9		T4	72
valid_sources[0x70]	298638	1			T2	16		T4	90		T11	24
valid_sources[0x71]	266823	1			T1	70		T2	9		T4	58
valid_sources[0x72]	258810	1			T1	94		T2	16		T4	91
valid_sources[0x73]	238581	1			T1	341		T2	9		T4	95
valid_sources[0x74]	240450	1			T1	224		T2	8		T4	129
valid_sources[0x75]	297763	1			T1	83		T2	18		T4	78
valid_sources[0x76]	255204	1			T1	216		T2	10		T4	15
valid_sources[0x77]	273184	1			T1	28		T2	5		T4	99
valid_sources[0x78]	271629	1			T1	257		T2	8		T4	76
valid_sources[0x79]	252372	1			T1	120		T2	21		T4	70
valid_sources[0x7a]	252588	1			T1	256		T2	8		T4	67
valid_sources[0x7b]	239384	1			T1	315		T2	1		T4	29
valid_sources[0x7c]	257976	1			T1	141		T2	8		T4	79
valid_sources[0x7d]	238738	1			T1	30		T2	13		T4	53
valid_sources[0x7e]	249689	1			T1	130		T4	141		T11	5
valid_sources[0x7f]	278961	1			T1	143		T2	2		T4	105
valid_sources[0x80]	269601	1			T1	218		T2	7		T4	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28217309

1

T1

31856

T2

6

T3

2476

values[0x0]

all_enables

biggest_size

14204053

1

T1

15735

T2

39

T3

1229

values[0x1]

all_enables

biggest_size

14207801

1

T1

15846

T2

50

T3

1297

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129726

1

T1

3

T4

4

T10

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48376	1			T4	3		T6	43		T7	33
values[0x0]	56126	1			T1	4		T3	1		T4	5
values[0x1]	60516	1			T1	4		T2	3		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138407

1

T1

6

T2

1

T4

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	681	1			T3	1		T28	2		T21	2
valid_sources[0x01]	616	1			T19	3		T133	1		T24	11
valid_sources[0x02]	728	1			T8	1		T144	1		T24	11
valid_sources[0x03]	491	1			T1	3		T38	1		T21	2
valid_sources[0x04]	664	1			T135	1		T133	3		T145	4
valid_sources[0x05]	808	1			T8	5		T40	1		T19	1
valid_sources[0x06]	486	1			T8	3		T19	1		T21	3
valid_sources[0x07]	865	1			T27	2		T44	1		T45	1
valid_sources[0x08]	587	1			T19	2		T146	1		T135	1
valid_sources[0x09]	1404	1			T19	1		T135	1		T147	2
valid_sources[0x0a]	791	1			T148	1		T25	19		T70	3
valid_sources[0x0b]	754	1			T149	1		T25	10		T137	1
valid_sources[0x0c]	590	1			T44	1		T142	1		T150	2
valid_sources[0x0d]	459	1			T38	2		T151	1		T19	1
valid_sources[0x0e]	651	1			T19	1		T146	1		T138	25
valid_sources[0x0f]	746	1			T8	2		T24	2		T68	2
valid_sources[0x10]	516	1			T8	3		T152	1		T19	1
valid_sources[0x11]	618	1			T19	1		T16	3		T135	1
valid_sources[0x12]	538	1			T44	1		T16	1		T21	1
valid_sources[0x13]	699	1			T1	4		T19	1		T17	3
valid_sources[0x14]	578	1			T44	1		T8	4		T19	1
valid_sources[0x15]	584	1			T106	4		T16	2		T133	1
valid_sources[0x16]	546	1			T8	4		T153	4		T138	2
valid_sources[0x17]	659	1			T8	1		T38	2		T21	2
valid_sources[0x18]	737	1			T106	2		T135	1		T154	2
valid_sources[0x19]	566	1			T19	2		T21	2		T155	3
valid_sources[0x1a]	545	1			T28	3		T19	1		T20	2
valid_sources[0x1b]	783	1			T38	1		T19	1		T17	1
valid_sources[0x1c]	540	1			T38	2		T21	1		T135	1
valid_sources[0x1d]	850	1			T19	2		T17	1		T16	1
valid_sources[0x1e]	732	1			T30	2		T43	1		T19	2
valid_sources[0x1f]	803	1			T38	2		T156	1		T20	1
valid_sources[0x20]	541	1			T10	5		T28	1		T19	1
valid_sources[0x21]	594	1			T19	1		T149	1		T21	3
valid_sources[0x22]	842	1			T7	13		T19	1		T133	1
valid_sources[0x23]	640	1			T41	3		T149	2		T21	1
valid_sources[0x24]	487	1			T19	1		T25	7		T157	1
valid_sources[0x25]	715	1			T17	1		T16	1		T25	16
valid_sources[0x26]	532	1			T21	1		T143	1		T89	1
valid_sources[0x27]	705	1			T42	1		T19	1		T139	1
valid_sources[0x28]	611	1			T158	1		T159	1		T24	19
valid_sources[0x29]	713	1			T8	4		T19	1		T17	1
valid_sources[0x2a]	614	1			T19	1		T133	1		T160	2
valid_sources[0x2b]	510	1			T19	1		T108	1		T138	4
valid_sources[0x2c]	715	1			T8	3		T21	1		T133	1
valid_sources[0x2d]	636	1			T27	1		T38	1		T142	1
valid_sources[0x2e]	542	1			T19	1		T133	1		T153	2
valid_sources[0x2f]	775	1			T38	4		T19	1		T135	2
valid_sources[0x30]	682	1			T29	3		T19	1		T142	1
valid_sources[0x31]	537	1			T161	17		T133	1		T20	1
valid_sources[0x32]	660	1			T19	1		T133	1		T158	1
valid_sources[0x33]	628	1			T8	2		T107	3		T24	1
valid_sources[0x34]	804	1			T19	2		T162	1		T135	1
valid_sources[0x35]	676	1			T8	5		T38	1		T19	2
valid_sources[0x36]	655	1			T61	2		T19	2		T17	3
valid_sources[0x37]	763	1			T152	1		T133	1		T148	1
valid_sources[0x38]	566	1			T8	1		T21	2		T135	1
valid_sources[0x39]	473	1			T19	2		T146	1		T21	2
valid_sources[0x3a]	520	1			T21	1		T143	1		T133	1
valid_sources[0x3b]	745	1			T142	2		T21	1		T20	1
valid_sources[0x3c]	695	1			T38	1		T19	1		T21	1
valid_sources[0x3d]	595	1			T152	1		T19	2		T163	2
valid_sources[0x3e]	541	1			T8	3		T19	1		T164	1
valid_sources[0x3f]	910	1			T44	1		T19	1		T135	1
valid_sources[0x40]	512	1			T19	2		T21	6		T108	1
valid_sources[0x41]	664	1			T19	2		T142	1		T21	1
valid_sources[0x42]	688	1			T19	1		T17	1		T158	1
valid_sources[0x43]	903	1			T8	4		T19	2		T165	1
valid_sources[0x44]	621	1			T21	1		T166	1		T167	1
valid_sources[0x45]	468	1			T19	1		T21	1		T139	1
valid_sources[0x46]	787	1			T16	1		T21	2		T135	2
valid_sources[0x47]	590	1			T151	1		T19	1		T21	1
valid_sources[0x48]	687	1			T27	1		T133	1		T24	4
valid_sources[0x49]	633	1			T158	1		T25	18		T168	2
valid_sources[0x4a]	598	1			T8	3		T162	1		T138	19
valid_sources[0x4b]	590	1			T15	2		T19	2		T21	1
valid_sources[0x4c]	726	1			T8	1		T21	1		T135	1
valid_sources[0x4d]	616	1			T39	1		T21	2		T20	1
valid_sources[0x4e]	564	1			T38	1		T19	2		T148	1
valid_sources[0x4f]	432	1			T7	4		T38	1		T21	1
valid_sources[0x50]	576	1			T8	1		T21	1		T145	1
valid_sources[0x51]	810	1			T8	4		T142	2		T21	1
valid_sources[0x52]	510	1			T2	3		T41	3		T46	1
valid_sources[0x53]	537	1			T44	1		T133	1		T165	1
valid_sources[0x54]	598	1			T7	1		T19	2		T139	1
valid_sources[0x55]	630	1			T21	5		T133	1		T150	24
valid_sources[0x56]	466	1			T8	1		T140	1		T169	10
valid_sources[0x57]	784	1			T5	1		T152	1		T21	2
valid_sources[0x58]	454	1			T44	1		T19	3		T21	1
valid_sources[0x59]	759	1			T44	2		T8	2		T151	1
valid_sources[0x5a]	651	1			T31	1		T8	2		T19	2
valid_sources[0x5b]	632	1			T138	4		T24	8		T18	1
valid_sources[0x5c]	517	1			T1	1		T44	1		T38	1
valid_sources[0x5d]	452	1			T44	1		T152	1		T19	1
valid_sources[0x5e]	579	1			T8	2		T19	2		T21	3
valid_sources[0x5f]	453	1			T38	1		T152	1		T19	1
valid_sources[0x60]	676	1			T19	1		T21	1		T150	2
valid_sources[0x61]	450	1			T19	1		T138	3		T25	16
valid_sources[0x62]	494	1			T27	4		T17	1		T146	2
valid_sources[0x63]	540	1			T8	2		T21	2		T20	2
valid_sources[0x64]	520	1			T28	3		T8	2		T19	1
valid_sources[0x65]	627	1			T19	2		T146	1		T165	1
valid_sources[0x66]	696	1			T44	1		T19	1		T170	1
valid_sources[0x67]	542	1			T14	2		T21	3		T50	1
valid_sources[0x68]	719	1			T8	3		T19	2		T21	2
valid_sources[0x69]	559	1			T19	2		T21	3		T135	2
valid_sources[0x6a]	660	1			T44	1		T21	1		T18	1
valid_sources[0x6b]	942	1			T38	1		T19	1		T21	2
valid_sources[0x6c]	671	1			T7	9		T8	1		T15	3
valid_sources[0x6d]	772	1			T19	2		T146	1		T144	1
valid_sources[0x6e]	635	1			T8	2		T19	2		T21	1
valid_sources[0x6f]	733	1			T19	1		T17	2		T159	1
valid_sources[0x70]	652	1			T8	2		T19	1		T135	1
valid_sources[0x71]	579	1			T27	1		T19	1		T21	1
valid_sources[0x72]	569	1			T27	1		T8	1		T20	1
valid_sources[0x73]	471	1			T8	3		T19	1		T142	1
valid_sources[0x74]	665	1			T19	2		T171	2		T172	1
valid_sources[0x75]	527	1			T5	1		T27	6		T19	2
valid_sources[0x76]	604	1			T20	1		T148	1		T25	24
valid_sources[0x77]	620	1			T17	1		T135	1		T25	23
valid_sources[0x78]	444	1			T19	1		T21	1		T138	3
valid_sources[0x79]	600	1			T8	1		T21	2		T165	1
valid_sources[0x7a]	654	1			T44	1		T8	3		T38	1
valid_sources[0x7b]	493	1			T21	3		T148	1		T25	23
valid_sources[0x7c]	446	1			T44	1		T38	1		T19	2
valid_sources[0x7d]	519	1			T38	1		T142	1		T21	1
valid_sources[0x7e]	1108	1			T19	1		T21	3		T24	1
valid_sources[0x7f]	629	1			T19	1		T21	1		T45	1
valid_sources[0x80]	632	1			T19	2		T21	2		T135	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35913

1

T4

1

T6

22

T7

20

values[0x0]

all_enables

biggest_size

47814

1

T1

2

T4

1

T10

5

values[0x1]

all_enables

biggest_size

45999

1

T1

1

T4

2

T6

13