Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13313166

1

T1

6382

T2

1813

T3

468

full_word

51826503

1

T1

63437

T2

95

T3

5002

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65139369	1			T1	69819		T2	1908		T3	5470
auto[TlIntgErrCmd]	97	1			T58	6		T59	4		T60	9
auto[TlIntgErrData]	96	1			T58	8		T59	8		T60	2
auto[TlIntgErrBoth]	107	1			T58	6		T59	8		T60	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29853731

1

T1

35086

T2

823

T3

2729

auto[1]

35285938

1

T1

34733

T2

1085

T3

2741

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6365435	1			T1	3230		T2	817		T3	253
auto[TlIntgErrNone]	partial	auto[1]	6947451	1			T1	3152		T2	996		T3	215
auto[TlIntgErrNone]	full_word	auto[0]	23488150	1			T1	31856		T2	6		T3	2476
auto[TlIntgErrNone]	full_word	auto[1]	28338333	1			T1	31581		T2	89		T3	2526
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T58	2		T60	4		T127	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T58	3		T59	2		T60	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T58	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T59	2		T60	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T58	5		T59	6		T60	1
auto[TlIntgErrData]	partial	auto[1]	35	1			T58	3		T59	1		T60	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T59	1		T122	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T124	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T58	1		T59	3		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T58	4		T59	4		T60	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T58	1		T122	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T59	1		T129	1		T125	1