Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	673027	1			T1	107		T4	3		T11	23
auto[1]	10277553	1			T1	921		T4	110		T5	39
auto[2]	560945	1			T1	58		T4	5		T11	11
auto[3]	10173723	1			T1	850		T4	77		T5	42

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14043639	1			T1	1380		T4	137		T5	81
auto[1]	2070901	1			T1	197		T4	25		T11	5
auto[2]	2085624	1			T1	330		T4	30		T11	14
auto[3]	3485084	1			T1	29		T4	3		T11	192

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8615087

1

T1

1935

T4

194

T5

81

auto[1]

13070161

1

T1

1

T4

1

T12

89539

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	242805	1			T1	88		T4	3		T13	1
auto[0]	auto[0]	auto[1]	24832	1			T1	8		T11	1		T6	32
auto[0]	auto[0]	auto[2]	24892	1			T1	10		T11	1		T6	21
auto[0]	auto[0]	auto[3]	6386	1			T11	21		T6	3		T28	2
auto[0]	auto[1]	auto[0]	3304431	1			T1	693		T4	83		T5	39
auto[0]	auto[1]	auto[1]	346313	1			T1	130		T4	17		T11	1
auto[0]	auto[1]	auto[2]	333976	1			T1	88		T4	8		T11	1
auto[0]	auto[1]	auto[3]	64334	1			T1	10		T4	1		T11	56
auto[0]	auto[2]	auto[0]	206746	1			T8	1		T38	4		T19	9398
auto[0]	auto[2]	auto[1]	21122	1			T19	957		T140	6		T134	19
auto[0]	auto[2]	auto[2]	23490	1			T1	53		T4	5		T6	189
auto[0]	auto[2]	auto[3]	5136	1			T1	5		T11	11		T6	16
auto[0]	auto[3]	auto[0]	3268655	1			T1	598		T4	51		T5	42
auto[0]	auto[3]	auto[1]	331098	1			T1	59		T4	8		T11	3
auto[0]	auto[3]	auto[2]	344754	1			T1	179		T4	16		T11	12
auto[0]	auto[3]	auto[3]	66117	1			T1	14		T4	2		T11	104
auto[1]	auto[0]	auto[0]	12815	1			T1	1		T19	14		T105	133
auto[1]	auto[0]	auto[1]	55567	1			T19	3		T105	555		T121	1927
auto[1]	auto[0]	auto[2]	55871	1			T105	568		T121	1888		T141	3
auto[1]	auto[0]	auto[3]	249859	1			T105	2668		T90	3		T91	4
auto[1]	auto[1]	auto[0]	3501335	1			T12	37223		T14	4		T29	2761
auto[1]	auto[1]	auto[1]	642950	1			T12	3628		T14	1		T29	12194
auto[1]	auto[1]	auto[2]	622756	1			T4	1		T12	3673		T14	1
auto[1]	auto[1]	auto[3]	1461458	1			T12	356		T14	1		T29	55317
auto[1]	auto[2]	auto[0]	9113	1			T19	6		T142	9		T143	11
auto[1]	auto[2]	auto[1]	39818	1			T19	1		T142	2		T143	2
auto[1]	auto[2]	auto[2]	46742	1			T105	476		T142	1		T143	2
auto[1]	auto[2]	auto[3]	208778	1			T19	1		T105	2381		T121	7097
auto[1]	auto[3]	auto[0]	3497739	1			T12	36887		T14	4		T29	2828
auto[1]	auto[3]	auto[1]	609201	1			T12	3703		T29	12522		T6	1
auto[1]	auto[3]	auto[2]	633143	1			T12	3708		T29	12473		T30	1
auto[1]	auto[3]	auto[3]	1423016	1			T12	361		T29	55296		T27	1