Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	293264321	197505	0	0
ctrl_regwen_rd_A	293264321	4308	0	0
exec_rd_A	293264321	3983	0	0
exec_regwen_rd_A	293264321	4590	0	0
readback_rd_A	293264321	3395	0	0
readback_regwen_rd_A	293264321	2936	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293264321	197505	0	0
T18	11966	0	0	0
T24	27194	1313	0	0
T25	214969	4956	0	0
T26	0	1789	0	0
T48	0	4695	0	0
T55	0	6000	0	0
T56	0	1556	0	0
T57	0	2118	0	0
T65	0	1925	0	0
T66	0	1840	0	0
T67	0	3141	0	0
T68	132763	0	0	0
T69	8161	0	0	0
T70	60026	0	0	0
T71	10219	0	0	0
T72	31151	0	0	0
T73	14695	0	0	0
T74	143953	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293264321	4308	0	0
T25	214969	399	0	0
T48	0	360	0	0
T56	0	112	0	0
T66	0	114	0	0
T69	8161	0	0	0
T70	60026	0	0	0
T71	10219	0	0	0
T72	31151	0	0	0
T73	14695	0	0	0
T74	143953	0	0	0
T113	0	211	0	0
T114	0	354	0	0
T115	0	293	0	0
T116	0	139	0	0
T117	0	496	0	0
T118	0	34	0	0
T119	136580	0	0	0
T120	9669	0	0	0
T121	759477	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293264321	3983	0	0
T25	214969	406	0	0
T48	0	301	0	0
T56	0	128	0	0
T66	0	145	0	0
T69	8161	0	0	0
T70	60026	0	0	0
T71	10219	0	0	0
T72	31151	0	0	0
T73	14695	0	0	0
T74	143953	0	0	0
T113	0	262	0	0
T114	0	222	0	0
T115	0	226	0	0
T116	0	88	0	0
T117	0	493	0	0
T118	0	35	0	0
T119	136580	0	0	0
T120	9669	0	0	0
T121	759477	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293264321	4590	0	0
T25	214969	501	0	0
T48	0	407	0	0
T56	0	140	0	0
T66	0	116	0	0
T69	8161	0	0	0
T70	60026	0	0	0
T71	10219	0	0	0
T72	31151	0	0	0
T73	14695	0	0	0
T74	143953	0	0	0
T113	0	281	0	0
T114	0	321	0	0
T115	0	252	0	0
T116	0	134	0	0
T117	0	400	0	0
T118	0	75	0	0
T119	136580	0	0	0
T120	9669	0	0	0
T121	759477	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293264321	3395	0	0
T25	214969	506	0	0
T48	0	343	0	0
T56	0	107	0	0
T66	0	99	0	0
T69	8161	0	0	0
T70	60026	0	0	0
T71	10219	0	0	0
T72	31151	0	0	0
T73	14695	0	0	0
T74	143953	0	0	0
T113	0	270	0	0
T114	0	277	0	0
T115	0	222	0	0
T116	0	144	0	0
T117	0	462	0	0
T118	0	39	0	0
T119	136580	0	0	0
T120	9669	0	0	0
T121	759477	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293264321	2936	0	0
T25	214969	357	0	0
T48	0	289	0	0
T56	0	137	0	0
T66	0	122	0	0
T69	8161	0	0	0
T70	60026	0	0	0
T71	10219	0	0	0
T72	31151	0	0	0
T73	14695	0	0	0
T74	143953	0	0	0
T113	0	257	0	0
T114	0	314	0	0
T115	0	222	0	0
T116	0	82	0	0
T117	0	348	0	0
T118	0	23	0	0
T119	136580	0	0	0
T120	9669	0	0	0
T121	759477	0	0	0