| T788 |
/workspace/coverage/default/34.sram_ctrl_smoke.4178657232 |
|
|
Aug 06 05:56:52 PM PDT 24 |
Aug 06 05:57:04 PM PDT 24 |
7959726582 ps |
| T789 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3933416045 |
|
|
Aug 06 05:53:55 PM PDT 24 |
Aug 06 06:13:49 PM PDT 24 |
10761609283 ps |
| T790 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.409553023 |
|
|
Aug 06 05:58:02 PM PDT 24 |
Aug 06 05:58:08 PM PDT 24 |
1011765031 ps |
| T791 |
/workspace/coverage/default/35.sram_ctrl_bijection.1272650993 |
|
|
Aug 06 05:57:03 PM PDT 24 |
Aug 06 05:57:50 PM PDT 24 |
2995709207 ps |
| T792 |
/workspace/coverage/default/28.sram_ctrl_smoke.3798023305 |
|
|
Aug 06 05:55:59 PM PDT 24 |
Aug 06 05:56:46 PM PDT 24 |
603311856 ps |
| T793 |
/workspace/coverage/default/20.sram_ctrl_alert_test.1499095835 |
|
|
Aug 06 05:55:10 PM PDT 24 |
Aug 06 05:55:11 PM PDT 24 |
20919675 ps |
| T794 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.509054203 |
|
|
Aug 06 05:57:47 PM PDT 24 |
Aug 06 05:57:57 PM PDT 24 |
462071101 ps |
| T795 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.15417210 |
|
|
Aug 06 05:54:42 PM PDT 24 |
Aug 06 05:54:53 PM PDT 24 |
1751652821 ps |
| T796 |
/workspace/coverage/default/6.sram_ctrl_bijection.2846813894 |
|
|
Aug 06 05:53:40 PM PDT 24 |
Aug 06 05:55:11 PM PDT 24 |
5994053372 ps |
| T797 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2678550363 |
|
|
Aug 06 05:53:57 PM PDT 24 |
Aug 06 05:56:28 PM PDT 24 |
306911186 ps |
| T798 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2872481462 |
|
|
Aug 06 05:56:40 PM PDT 24 |
Aug 06 05:56:47 PM PDT 24 |
1371380713 ps |
| T799 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3416172670 |
|
|
Aug 06 05:56:13 PM PDT 24 |
Aug 06 05:57:49 PM PDT 24 |
6623883087 ps |
| T800 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2333858337 |
|
|
Aug 06 05:57:47 PM PDT 24 |
Aug 06 06:55:17 PM PDT 24 |
118375613060 ps |
| T801 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.372176128 |
|
|
Aug 06 05:55:58 PM PDT 24 |
Aug 06 06:17:02 PM PDT 24 |
11396905551 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1052520388 |
|
|
Aug 06 05:53:59 PM PDT 24 |
Aug 06 05:53:59 PM PDT 24 |
44917012 ps |
| T803 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3945203481 |
|
|
Aug 06 05:56:09 PM PDT 24 |
Aug 06 05:56:14 PM PDT 24 |
341988408 ps |
| T804 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.298053293 |
|
|
Aug 06 05:53:58 PM PDT 24 |
Aug 06 05:53:59 PM PDT 24 |
39920880 ps |
| T805 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.525096231 |
|
|
Aug 06 05:55:07 PM PDT 24 |
Aug 06 05:56:57 PM PDT 24 |
146663602 ps |
| T806 |
/workspace/coverage/default/8.sram_ctrl_alert_test.886846616 |
|
|
Aug 06 05:53:56 PM PDT 24 |
Aug 06 05:53:57 PM PDT 24 |
43391038 ps |
| T807 |
/workspace/coverage/default/23.sram_ctrl_regwen.2023564526 |
|
|
Aug 06 05:55:20 PM PDT 24 |
Aug 06 06:24:44 PM PDT 24 |
92096665695 ps |
| T808 |
/workspace/coverage/default/49.sram_ctrl_executable.702582423 |
|
|
Aug 06 05:59:54 PM PDT 24 |
Aug 06 06:13:36 PM PDT 24 |
1485105528 ps |
| T809 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.304013618 |
|
|
Aug 06 05:56:51 PM PDT 24 |
Aug 06 05:56:53 PM PDT 24 |
138389959 ps |
| T810 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1854412070 |
|
|
Aug 06 05:58:57 PM PDT 24 |
Aug 06 06:17:24 PM PDT 24 |
6857608228 ps |
| T811 |
/workspace/coverage/default/42.sram_ctrl_smoke.3232031675 |
|
|
Aug 06 05:58:16 PM PDT 24 |
Aug 06 05:59:47 PM PDT 24 |
693916507 ps |
| T812 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.33450801 |
|
|
Aug 06 05:53:35 PM PDT 24 |
Aug 06 05:57:15 PM PDT 24 |
12108695696 ps |
| T813 |
/workspace/coverage/default/27.sram_ctrl_bijection.71142002 |
|
|
Aug 06 05:55:45 PM PDT 24 |
Aug 06 05:57:01 PM PDT 24 |
13322137658 ps |
| T814 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2824014671 |
|
|
Aug 06 05:56:24 PM PDT 24 |
Aug 06 05:56:27 PM PDT 24 |
49633431 ps |
| T815 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1748256657 |
|
|
Aug 06 05:53:54 PM PDT 24 |
Aug 06 05:54:00 PM PDT 24 |
175985807 ps |
| T816 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.122904464 |
|
|
Aug 06 05:59:29 PM PDT 24 |
Aug 06 05:59:30 PM PDT 24 |
34686406 ps |
| T817 |
/workspace/coverage/default/21.sram_ctrl_bijection.1894227015 |
|
|
Aug 06 05:55:07 PM PDT 24 |
Aug 06 05:55:33 PM PDT 24 |
1656208592 ps |
| T818 |
/workspace/coverage/default/32.sram_ctrl_bijection.158287734 |
|
|
Aug 06 05:56:37 PM PDT 24 |
Aug 06 05:57:28 PM PDT 24 |
4354734909 ps |
| T819 |
/workspace/coverage/default/43.sram_ctrl_bijection.1957075042 |
|
|
Aug 06 05:58:29 PM PDT 24 |
Aug 06 05:59:04 PM PDT 24 |
2131992084 ps |
| T820 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2859938849 |
|
|
Aug 06 05:53:40 PM PDT 24 |
Aug 06 05:57:13 PM PDT 24 |
9466892593 ps |
| T821 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3693769551 |
|
|
Aug 06 05:58:15 PM PDT 24 |
Aug 06 05:58:22 PM PDT 24 |
2195116793 ps |
| T822 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.4061356266 |
|
|
Aug 06 05:55:47 PM PDT 24 |
Aug 06 06:23:35 PM PDT 24 |
33359989452 ps |
| T823 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1108504973 |
|
|
Aug 06 05:59:51 PM PDT 24 |
Aug 06 06:03:49 PM PDT 24 |
3065312919 ps |
| T824 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.944144370 |
|
|
Aug 06 05:57:20 PM PDT 24 |
Aug 06 05:57:26 PM PDT 24 |
630000804 ps |
| T825 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3389091666 |
|
|
Aug 06 05:55:19 PM PDT 24 |
Aug 06 05:57:33 PM PDT 24 |
6663680307 ps |
| T826 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2643953462 |
|
|
Aug 06 05:55:32 PM PDT 24 |
Aug 06 05:55:42 PM PDT 24 |
2879554824 ps |
| T827 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2999161162 |
|
|
Aug 06 05:55:44 PM PDT 24 |
Aug 06 05:55:48 PM PDT 24 |
687274474 ps |
| T828 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3250775436 |
|
|
Aug 06 05:55:07 PM PDT 24 |
Aug 06 05:59:49 PM PDT 24 |
43712313475 ps |
| T829 |
/workspace/coverage/default/5.sram_ctrl_bijection.1190795575 |
|
|
Aug 06 05:53:28 PM PDT 24 |
Aug 06 05:54:16 PM PDT 24 |
2893379443 ps |
| T830 |
/workspace/coverage/default/45.sram_ctrl_regwen.1491256431 |
|
|
Aug 06 05:58:57 PM PDT 24 |
Aug 06 06:20:17 PM PDT 24 |
3058932381 ps |
| T831 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1147789668 |
|
|
Aug 06 06:00:06 PM PDT 24 |
Aug 06 06:00:51 PM PDT 24 |
606942248 ps |
| T832 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3213657352 |
|
|
Aug 06 05:58:15 PM PDT 24 |
Aug 06 06:01:22 PM PDT 24 |
10355459109 ps |
| T833 |
/workspace/coverage/default/49.sram_ctrl_bijection.2434338043 |
|
|
Aug 06 05:59:52 PM PDT 24 |
Aug 06 06:01:06 PM PDT 24 |
8865752377 ps |
| T834 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3559634639 |
|
|
Aug 06 05:55:15 PM PDT 24 |
Aug 06 06:00:05 PM PDT 24 |
21246631085 ps |
| T835 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.4018931304 |
|
|
Aug 06 05:54:44 PM PDT 24 |
Aug 06 05:54:44 PM PDT 24 |
46711870 ps |
| T836 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.499441251 |
|
|
Aug 06 05:53:55 PM PDT 24 |
Aug 06 05:53:57 PM PDT 24 |
1207291293 ps |
| T837 |
/workspace/coverage/default/18.sram_ctrl_executable.2985742856 |
|
|
Aug 06 05:54:41 PM PDT 24 |
Aug 06 05:57:09 PM PDT 24 |
1474167027 ps |
| T838 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.972124622 |
|
|
Aug 06 05:58:43 PM PDT 24 |
Aug 06 05:58:50 PM PDT 24 |
2598319716 ps |
| T839 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.88079735 |
|
|
Aug 06 05:56:51 PM PDT 24 |
Aug 06 05:57:02 PM PDT 24 |
242601955 ps |
| T840 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1191293962 |
|
|
Aug 06 05:53:07 PM PDT 24 |
Aug 06 06:16:15 PM PDT 24 |
6017606877 ps |
| T841 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1279964973 |
|
|
Aug 06 05:58:44 PM PDT 24 |
Aug 06 06:02:40 PM PDT 24 |
1678123196 ps |
| T842 |
/workspace/coverage/default/22.sram_ctrl_partial_access.3791532968 |
|
|
Aug 06 05:55:19 PM PDT 24 |
Aug 06 05:55:32 PM PDT 24 |
253283126 ps |
| T843 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2484729854 |
|
|
Aug 06 05:56:50 PM PDT 24 |
Aug 06 05:56:51 PM PDT 24 |
45742769 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2801119969 |
|
|
Aug 06 05:56:50 PM PDT 24 |
Aug 06 06:17:36 PM PDT 24 |
40557836213 ps |
| T845 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1514881989 |
|
|
Aug 06 05:57:21 PM PDT 24 |
Aug 06 06:05:01 PM PDT 24 |
34654424485 ps |
| T846 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2314921593 |
|
|
Aug 06 05:57:34 PM PDT 24 |
Aug 06 05:57:42 PM PDT 24 |
3684199595 ps |
| T847 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.216764026 |
|
|
Aug 06 05:55:14 PM PDT 24 |
Aug 06 06:08:19 PM PDT 24 |
13333389941 ps |
| T848 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2031489587 |
|
|
Aug 06 05:55:05 PM PDT 24 |
Aug 06 06:13:32 PM PDT 24 |
126810499927 ps |
| T849 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.559278780 |
|
|
Aug 06 05:57:47 PM PDT 24 |
Aug 06 05:59:08 PM PDT 24 |
134551969 ps |
| T850 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1985445791 |
|
|
Aug 06 05:58:15 PM PDT 24 |
Aug 06 06:05:42 PM PDT 24 |
4319009088 ps |
| T851 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1694384259 |
|
|
Aug 06 05:59:51 PM PDT 24 |
Aug 06 06:06:16 PM PDT 24 |
27504999120 ps |
| T852 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1757277380 |
|
|
Aug 06 05:59:11 PM PDT 24 |
Aug 06 05:59:12 PM PDT 24 |
45543252 ps |
| T853 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2807415065 |
|
|
Aug 06 05:58:54 PM PDT 24 |
Aug 06 05:59:54 PM PDT 24 |
664314295 ps |
| T854 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.1948881121 |
|
|
Aug 06 05:53:38 PM PDT 24 |
Aug 06 05:53:45 PM PDT 24 |
3696183637 ps |
| T855 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3903542404 |
|
|
Aug 06 05:53:57 PM PDT 24 |
Aug 06 05:54:52 PM PDT 24 |
436043352 ps |
| T856 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3501158529 |
|
|
Aug 06 05:58:28 PM PDT 24 |
Aug 06 05:58:35 PM PDT 24 |
593162281 ps |
| T857 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2990972056 |
|
|
Aug 06 05:56:50 PM PDT 24 |
Aug 06 05:56:52 PM PDT 24 |
81326825 ps |
| T858 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1271774703 |
|
|
Aug 06 05:53:41 PM PDT 24 |
Aug 06 05:53:49 PM PDT 24 |
1306296387 ps |
| T859 |
/workspace/coverage/default/1.sram_ctrl_regwen.1107447237 |
|
|
Aug 06 05:53:05 PM PDT 24 |
Aug 06 05:56:04 PM PDT 24 |
5292104537 ps |
| T860 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3889610848 |
|
|
Aug 06 05:53:09 PM PDT 24 |
Aug 06 05:53:25 PM PDT 24 |
314935132 ps |
| T861 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.90189856 |
|
|
Aug 06 05:53:38 PM PDT 24 |
Aug 06 05:53:42 PM PDT 24 |
1022180968 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3545504002 |
|
|
Aug 06 05:55:06 PM PDT 24 |
Aug 06 05:55:51 PM PDT 24 |
402749257 ps |
| T863 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2246981479 |
|
|
Aug 06 05:55:47 PM PDT 24 |
Aug 06 05:57:27 PM PDT 24 |
480985657 ps |
| T864 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1304959079 |
|
|
Aug 06 05:58:58 PM PDT 24 |
Aug 06 05:59:04 PM PDT 24 |
154089443 ps |
| T865 |
/workspace/coverage/default/16.sram_ctrl_executable.3866308511 |
|
|
Aug 06 05:54:29 PM PDT 24 |
Aug 06 06:03:31 PM PDT 24 |
2938027410 ps |
| T866 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1054642755 |
|
|
Aug 06 05:56:37 PM PDT 24 |
Aug 06 05:56:40 PM PDT 24 |
1000713787 ps |
| T867 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2600252658 |
|
|
Aug 06 05:58:43 PM PDT 24 |
Aug 06 06:01:04 PM PDT 24 |
388334670 ps |
| T868 |
/workspace/coverage/default/6.sram_ctrl_stress_all.114962764 |
|
|
Aug 06 05:53:40 PM PDT 24 |
Aug 06 06:34:16 PM PDT 24 |
34238292980 ps |
| T869 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2915184693 |
|
|
Aug 06 05:53:39 PM PDT 24 |
Aug 06 05:58:08 PM PDT 24 |
956249544 ps |
| T870 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1147070484 |
|
|
Aug 06 05:55:30 PM PDT 24 |
Aug 06 05:55:35 PM PDT 24 |
357541495 ps |
| T871 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2518928180 |
|
|
Aug 06 05:55:45 PM PDT 24 |
Aug 06 05:59:42 PM PDT 24 |
2531656640 ps |
| T872 |
/workspace/coverage/default/36.sram_ctrl_smoke.1361688123 |
|
|
Aug 06 05:57:20 PM PDT 24 |
Aug 06 05:59:13 PM PDT 24 |
579424685 ps |
| T873 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1483135552 |
|
|
Aug 06 05:56:26 PM PDT 24 |
Aug 06 06:01:58 PM PDT 24 |
46667262469 ps |
| T874 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.429735053 |
|
|
Aug 06 05:59:11 PM PDT 24 |
Aug 06 06:11:58 PM PDT 24 |
43036915362 ps |
| T875 |
/workspace/coverage/default/9.sram_ctrl_regwen.4108897785 |
|
|
Aug 06 05:54:05 PM PDT 24 |
Aug 06 06:13:40 PM PDT 24 |
59180204924 ps |
| T876 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3852444105 |
|
|
Aug 06 05:55:59 PM PDT 24 |
Aug 06 05:55:59 PM PDT 24 |
16196969 ps |
| T877 |
/workspace/coverage/default/7.sram_ctrl_smoke.595255536 |
|
|
Aug 06 05:53:38 PM PDT 24 |
Aug 06 05:53:43 PM PDT 24 |
119183256 ps |
| T878 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2169722393 |
|
|
Aug 06 05:56:37 PM PDT 24 |
Aug 06 05:59:28 PM PDT 24 |
6987677755 ps |
| T879 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.971563767 |
|
|
Aug 06 05:53:55 PM PDT 24 |
Aug 06 05:53:56 PM PDT 24 |
46810269 ps |
| T880 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3126885813 |
|
|
Aug 06 05:53:07 PM PDT 24 |
Aug 06 05:59:50 PM PDT 24 |
1884643104 ps |
| T881 |
/workspace/coverage/default/0.sram_ctrl_smoke.1261694784 |
|
|
Aug 06 05:53:08 PM PDT 24 |
Aug 06 05:53:19 PM PDT 24 |
649036870 ps |
| T882 |
/workspace/coverage/default/12.sram_ctrl_executable.154428914 |
|
|
Aug 06 05:54:00 PM PDT 24 |
Aug 06 06:10:04 PM PDT 24 |
38683857268 ps |
| T883 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3483070924 |
|
|
Aug 06 05:55:47 PM PDT 24 |
Aug 06 06:01:01 PM PDT 24 |
48390700122 ps |
| T884 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1085031429 |
|
|
Aug 06 05:59:28 PM PDT 24 |
Aug 06 05:59:32 PM PDT 24 |
736470056 ps |
| T885 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2901888763 |
|
|
Aug 06 05:54:45 PM PDT 24 |
Aug 06 05:54:54 PM PDT 24 |
526910832 ps |
| T886 |
/workspace/coverage/default/42.sram_ctrl_regwen.963374271 |
|
|
Aug 06 05:58:29 PM PDT 24 |
Aug 06 06:08:31 PM PDT 24 |
3723752336 ps |
| T887 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3739896160 |
|
|
Aug 06 05:55:57 PM PDT 24 |
Aug 06 05:56:04 PM PDT 24 |
308488600 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_alert_test.516170152 |
|
|
Aug 06 05:57:33 PM PDT 24 |
Aug 06 05:57:34 PM PDT 24 |
79764026 ps |
| T889 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2743596247 |
|
|
Aug 06 05:53:56 PM PDT 24 |
Aug 06 05:53:57 PM PDT 24 |
74974087 ps |
| T890 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3193111524 |
|
|
Aug 06 05:55:17 PM PDT 24 |
Aug 06 05:57:08 PM PDT 24 |
124637334 ps |
| T891 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3345391924 |
|
|
Aug 06 05:54:27 PM PDT 24 |
Aug 06 06:35:10 PM PDT 24 |
190352914880 ps |
| T892 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1301755417 |
|
|
Aug 06 05:58:01 PM PDT 24 |
Aug 06 06:04:01 PM PDT 24 |
7487771303 ps |
| T893 |
/workspace/coverage/default/10.sram_ctrl_stress_all.4006650437 |
|
|
Aug 06 05:54:03 PM PDT 24 |
Aug 06 06:15:00 PM PDT 24 |
26430991785 ps |
| T894 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3131989576 |
|
|
Aug 06 05:53:10 PM PDT 24 |
Aug 06 05:53:49 PM PDT 24 |
101171478 ps |
| T895 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.193398817 |
|
|
Aug 06 05:59:13 PM PDT 24 |
Aug 06 06:04:06 PM PDT 24 |
11651838623 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1911324182 |
|
|
Aug 06 05:54:41 PM PDT 24 |
Aug 06 05:58:48 PM PDT 24 |
2573394521 ps |
| T897 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3956522535 |
|
|
Aug 06 05:57:01 PM PDT 24 |
Aug 06 05:58:07 PM PDT 24 |
135011109 ps |
| T898 |
/workspace/coverage/default/3.sram_ctrl_smoke.943021062 |
|
|
Aug 06 05:53:03 PM PDT 24 |
Aug 06 05:53:08 PM PDT 24 |
246763099 ps |
| T899 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3089196135 |
|
|
Aug 06 05:53:10 PM PDT 24 |
Aug 06 05:53:11 PM PDT 24 |
31207108 ps |
| T900 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3557948078 |
|
|
Aug 06 05:58:14 PM PDT 24 |
Aug 06 06:11:37 PM PDT 24 |
9335396575 ps |
| T901 |
/workspace/coverage/default/27.sram_ctrl_partial_access.925191455 |
|
|
Aug 06 05:55:59 PM PDT 24 |
Aug 06 05:56:06 PM PDT 24 |
763550611 ps |
| T902 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2785331586 |
|
|
Aug 06 05:55:32 PM PDT 24 |
Aug 06 05:55:32 PM PDT 24 |
49359697 ps |
| T903 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1430708660 |
|
|
Aug 06 05:53:07 PM PDT 24 |
Aug 06 05:55:58 PM PDT 24 |
4012310716 ps |
| T904 |
/workspace/coverage/default/25.sram_ctrl_bijection.2890191409 |
|
|
Aug 06 05:55:34 PM PDT 24 |
Aug 06 05:56:10 PM PDT 24 |
635864608 ps |
| T905 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1780989147 |
|
|
Aug 06 05:56:11 PM PDT 24 |
Aug 06 05:56:21 PM PDT 24 |
3635069785 ps |
| T906 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3958414556 |
|
|
Aug 06 05:55:17 PM PDT 24 |
Aug 06 05:55:18 PM PDT 24 |
32504620 ps |
| T907 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.696415897 |
|
|
Aug 06 05:54:00 PM PDT 24 |
Aug 06 05:54:23 PM PDT 24 |
1021635681 ps |
| T908 |
/workspace/coverage/default/14.sram_ctrl_executable.3292116087 |
|
|
Aug 06 05:54:21 PM PDT 24 |
Aug 06 06:01:56 PM PDT 24 |
2996236865 ps |
| T909 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3664850490 |
|
|
Aug 06 05:58:27 PM PDT 24 |
Aug 06 05:58:30 PM PDT 24 |
84135755 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1102733156 |
|
|
Aug 06 05:55:48 PM PDT 24 |
Aug 06 05:55:51 PM PDT 24 |
56735156 ps |
| T911 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1389169859 |
|
|
Aug 06 05:54:15 PM PDT 24 |
Aug 06 05:54:21 PM PDT 24 |
233044177 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3558323510 |
|
|
Aug 06 06:00:06 PM PDT 24 |
Aug 06 06:14:35 PM PDT 24 |
72096557159 ps |
| T913 |
/workspace/coverage/default/35.sram_ctrl_executable.711445071 |
|
|
Aug 06 05:57:05 PM PDT 24 |
Aug 06 06:32:01 PM PDT 24 |
15640780250 ps |
| T914 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2002503789 |
|
|
Aug 06 05:53:57 PM PDT 24 |
Aug 06 05:55:01 PM PDT 24 |
849777525 ps |
| T915 |
/workspace/coverage/default/32.sram_ctrl_alert_test.398265079 |
|
|
Aug 06 05:56:35 PM PDT 24 |
Aug 06 05:56:36 PM PDT 24 |
18058195 ps |
| T916 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.265658734 |
|
|
Aug 06 05:54:02 PM PDT 24 |
Aug 06 05:54:29 PM PDT 24 |
9784584015 ps |
| T917 |
/workspace/coverage/default/22.sram_ctrl_bijection.3223914784 |
|
|
Aug 06 05:55:16 PM PDT 24 |
Aug 06 05:56:11 PM PDT 24 |
4873721279 ps |
| T918 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3534906824 |
|
|
Aug 06 05:54:42 PM PDT 24 |
Aug 06 05:58:08 PM PDT 24 |
1066983640 ps |
| T919 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2486057681 |
|
|
Aug 06 05:58:27 PM PDT 24 |
Aug 06 06:03:35 PM PDT 24 |
44669978413 ps |
| T920 |
/workspace/coverage/default/4.sram_ctrl_bijection.2864863416 |
|
|
Aug 06 05:53:35 PM PDT 24 |
Aug 06 05:54:05 PM PDT 24 |
486033042 ps |
| T921 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1784527692 |
|
|
Aug 06 05:54:40 PM PDT 24 |
Aug 06 05:54:50 PM PDT 24 |
1147601502 ps |
| T922 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.29785385 |
|
|
Aug 06 05:53:39 PM PDT 24 |
Aug 06 05:53:45 PM PDT 24 |
525426640 ps |
| T923 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2369486645 |
|
|
Aug 06 05:53:38 PM PDT 24 |
Aug 06 05:59:53 PM PDT 24 |
1813604753 ps |
| T924 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.840811740 |
|
|
Aug 06 05:57:47 PM PDT 24 |
Aug 06 05:57:48 PM PDT 24 |
30594578 ps |
| T925 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2407538069 |
|
|
Aug 06 05:53:30 PM PDT 24 |
Aug 06 05:53:31 PM PDT 24 |
51715251 ps |
| T926 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1185670287 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
58808058 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3455173568 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:31 PM PDT 24 |
20259902 ps |
| T63 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3376636079 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:49 PM PDT 24 |
380962678 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2372217568 |
|
|
Aug 06 05:39:08 PM PDT 24 |
Aug 06 05:39:10 PM PDT 24 |
270982885 ps |
| T58 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3017980477 |
|
|
Aug 06 05:39:26 PM PDT 24 |
Aug 06 05:39:29 PM PDT 24 |
299191210 ps |
| T927 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2374753433 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:32 PM PDT 24 |
45869842 ps |
| T928 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.872087854 |
|
|
Aug 06 05:39:24 PM PDT 24 |
Aug 06 05:39:25 PM PDT 24 |
25400521 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3706120545 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:31 PM PDT 24 |
65194453 ps |
| T929 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1205190085 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:06 PM PDT 24 |
41765392 ps |
| T930 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2989819047 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:28 PM PDT 24 |
487199940 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1679961414 |
|
|
Aug 06 05:39:28 PM PDT 24 |
Aug 06 05:39:29 PM PDT 24 |
22656627 ps |
| T76 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1079276471 |
|
|
Aug 06 05:39:26 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
22179099 ps |
| T931 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2872031605 |
|
|
Aug 06 05:40:02 PM PDT 24 |
Aug 06 05:40:04 PM PDT 24 |
37245058 ps |
| T932 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3224502782 |
|
|
Aug 06 05:40:03 PM PDT 24 |
Aug 06 05:40:05 PM PDT 24 |
33919518 ps |
| T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2553913918 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
14345630 ps |
| T933 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2461128988 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:49 PM PDT 24 |
62277787 ps |
| T934 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1193953889 |
|
|
Aug 06 05:39:26 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
34355260 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1646940836 |
|
|
Aug 06 05:39:09 PM PDT 24 |
Aug 06 05:39:09 PM PDT 24 |
15652456 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.918204549 |
|
|
Aug 06 05:39:28 PM PDT 24 |
Aug 06 05:39:30 PM PDT 24 |
1430328107 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4280138501 |
|
|
Aug 06 05:39:11 PM PDT 24 |
Aug 06 05:39:13 PM PDT 24 |
1170554041 ps |
| T80 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3744384009 |
|
|
Aug 06 05:39:11 PM PDT 24 |
Aug 06 05:39:12 PM PDT 24 |
31593889 ps |
| T935 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2120139244 |
|
|
Aug 06 05:39:29 PM PDT 24 |
Aug 06 05:39:34 PM PDT 24 |
522391855 ps |
| T936 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.790971553 |
|
|
Aug 06 05:40:05 PM PDT 24 |
Aug 06 05:40:09 PM PDT 24 |
42508193 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3282514439 |
|
|
Aug 06 05:39:24 PM PDT 24 |
Aug 06 05:39:29 PM PDT 24 |
658611256 ps |
| T81 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1914811829 |
|
|
Aug 06 05:39:26 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
55600185 ps |
| T82 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3069213398 |
|
|
Aug 06 05:39:10 PM PDT 24 |
Aug 06 05:39:13 PM PDT 24 |
456355282 ps |
| T59 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1063604274 |
|
|
Aug 06 05:39:48 PM PDT 24 |
Aug 06 05:39:50 PM PDT 24 |
177888838 ps |
| T104 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2705982860 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:04 PM PDT 24 |
17892930 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4069261661 |
|
|
Aug 06 05:39:28 PM PDT 24 |
Aug 06 05:39:29 PM PDT 24 |
19700136 ps |
| T60 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2322179673 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:50 PM PDT 24 |
652175803 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.519819773 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
400220668 ps |
| T127 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1196132095 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:49 PM PDT 24 |
294314862 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2935089046 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
397895570 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2340246723 |
|
|
Aug 06 05:39:08 PM PDT 24 |
Aug 06 05:39:11 PM PDT 24 |
274042266 ps |
| T939 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3596987884 |
|
|
Aug 06 05:39:09 PM PDT 24 |
Aug 06 05:39:12 PM PDT 24 |
34138382 ps |
| T940 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1169764927 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:04 PM PDT 24 |
19237353 ps |
| T941 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2788490180 |
|
|
Aug 06 05:40:06 PM PDT 24 |
Aug 06 05:40:07 PM PDT 24 |
20834777 ps |
| T942 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2289947020 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
153589098 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2597798757 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:09 PM PDT 24 |
549163732 ps |
| T944 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3080962732 |
|
|
Aug 06 05:39:28 PM PDT 24 |
Aug 06 05:39:30 PM PDT 24 |
127890876 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2623799205 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
24442561 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.310831912 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:26 PM PDT 24 |
64316597 ps |
| T946 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.853365806 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
51589403 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4034662102 |
|
|
Aug 06 05:39:08 PM PDT 24 |
Aug 06 05:39:10 PM PDT 24 |
457671014 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1690230903 |
|
|
Aug 06 05:40:03 PM PDT 24 |
Aug 06 05:40:05 PM PDT 24 |
821110617 ps |
| T947 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2989236399 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
240366308 ps |
| T948 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3358496867 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
36068079 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3056450414 |
|
|
Aug 06 05:39:11 PM PDT 24 |
Aug 06 05:39:12 PM PDT 24 |
49777804 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3203992495 |
|
|
Aug 06 05:39:50 PM PDT 24 |
Aug 06 05:39:51 PM PDT 24 |
30367907 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1265943818 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:50 PM PDT 24 |
378441433 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3860213160 |
|
|
Aug 06 05:40:03 PM PDT 24 |
Aug 06 05:40:04 PM PDT 24 |
69066192 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.337065114 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:08 PM PDT 24 |
434767113 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3591280013 |
|
|
Aug 06 05:39:27 PM PDT 24 |
Aug 06 05:39:28 PM PDT 24 |
77097086 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4094474539 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
73781266 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1060546716 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
14390966 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1895812078 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:26 PM PDT 24 |
30246120 ps |
| T97 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2062300323 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:50 PM PDT 24 |
828972764 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3796420257 |
|
|
Aug 06 05:40:05 PM PDT 24 |
Aug 06 05:40:07 PM PDT 24 |
329478310 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1918316385 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
111008184 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1993572256 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:49 PM PDT 24 |
315116107 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2023487770 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
11840055 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1696052310 |
|
|
Aug 06 05:39:50 PM PDT 24 |
Aug 06 05:39:52 PM PDT 24 |
339442035 ps |
| T123 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.161400868 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
189591809 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4196710928 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
12048110 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3192388834 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:31 PM PDT 24 |
16225647 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2402017589 |
|
|
Aug 06 05:40:03 PM PDT 24 |
Aug 06 05:40:05 PM PDT 24 |
64145162 ps |
| T963 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2579216259 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
42242308 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1752475792 |
|
|
Aug 06 05:39:24 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
132611479 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3476481632 |
|
|
Aug 06 05:40:02 PM PDT 24 |
Aug 06 05:40:04 PM PDT 24 |
25549246 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3580959444 |
|
|
Aug 06 05:39:09 PM PDT 24 |
Aug 06 05:39:10 PM PDT 24 |
34979931 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4154320986 |
|
|
Aug 06 05:39:08 PM PDT 24 |
Aug 06 05:39:12 PM PDT 24 |
147348572 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.38704340 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:28 PM PDT 24 |
766671204 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.462222881 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:49 PM PDT 24 |
211484802 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3994466084 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:30 PM PDT 24 |
38967659 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1132218043 |
|
|
Aug 06 05:40:02 PM PDT 24 |
Aug 06 05:40:02 PM PDT 24 |
20063278 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3910686774 |
|
|
Aug 06 05:40:06 PM PDT 24 |
Aug 06 05:40:07 PM PDT 24 |
54124276 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3153062681 |
|
|
Aug 06 05:40:02 PM PDT 24 |
Aug 06 05:40:03 PM PDT 24 |
29809272 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3240858691 |
|
|
Aug 06 05:39:09 PM PDT 24 |
Aug 06 05:39:10 PM PDT 24 |
15867179 ps |
| T124 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1986844605 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:32 PM PDT 24 |
243079298 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2262880489 |
|
|
Aug 06 05:40:02 PM PDT 24 |
Aug 06 05:40:03 PM PDT 24 |
237492176 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1632750814 |
|
|
Aug 06 05:39:26 PM PDT 24 |
Aug 06 05:39:30 PM PDT 24 |
2754367442 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4081536857 |
|
|
Aug 06 05:39:27 PM PDT 24 |
Aug 06 05:39:29 PM PDT 24 |
127674644 ps |
| T129 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2716572037 |
|
|
Aug 06 05:39:27 PM PDT 24 |
Aug 06 05:39:29 PM PDT 24 |
258400272 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2941207770 |
|
|
Aug 06 05:40:03 PM PDT 24 |
Aug 06 05:40:06 PM PDT 24 |
430489403 ps |
| T976 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1515009405 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:05 PM PDT 24 |
15622881 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3110142777 |
|
|
Aug 06 05:40:05 PM PDT 24 |
Aug 06 05:40:06 PM PDT 24 |
52831547 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1997466310 |
|
|
Aug 06 05:39:31 PM PDT 24 |
Aug 06 05:39:35 PM PDT 24 |
570082544 ps |
| T979 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.768287718 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
273796677 ps |
| T102 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1730870820 |
|
|
Aug 06 05:40:04 PM PDT 24 |
Aug 06 05:40:07 PM PDT 24 |
416868181 ps |
| T980 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3963322601 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
198573245 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2253600589 |
|
|
Aug 06 05:39:27 PM PDT 24 |
Aug 06 05:39:28 PM PDT 24 |
30116944 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.549561623 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
394478522 ps |
| T983 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2779672982 |
|
|
Aug 06 05:39:45 PM PDT 24 |
Aug 06 05:39:46 PM PDT 24 |
39124400 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4076770245 |
|
|
Aug 06 05:39:29 PM PDT 24 |
Aug 06 05:39:30 PM PDT 24 |
20448861 ps |
| T985 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4281869359 |
|
|
Aug 06 05:39:48 PM PDT 24 |
Aug 06 05:39:52 PM PDT 24 |
38296942 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2956251448 |
|
|
Aug 06 05:40:02 PM PDT 24 |
Aug 06 05:40:03 PM PDT 24 |
55572097 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1333055739 |
|
|
Aug 06 05:39:25 PM PDT 24 |
Aug 06 05:39:25 PM PDT 24 |
102071599 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1280007371 |
|
|
Aug 06 05:40:01 PM PDT 24 |
Aug 06 05:40:03 PM PDT 24 |
66657506 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.352730809 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
13304235 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1861005529 |
|
|
Aug 06 05:39:09 PM PDT 24 |
Aug 06 05:39:10 PM PDT 24 |
226261337 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.777915796 |
|
|
Aug 06 05:39:24 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
276226885 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3356943532 |
|
|
Aug 06 05:39:27 PM PDT 24 |
Aug 06 05:39:27 PM PDT 24 |
78453597 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.888928618 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
41685474 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3015005666 |
|
|
Aug 06 05:39:11 PM PDT 24 |
Aug 06 05:39:12 PM PDT 24 |
94241487 ps |
| T995 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2583846501 |
|
|
Aug 06 05:40:06 PM PDT 24 |
Aug 06 05:40:08 PM PDT 24 |
743903967 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3176121159 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:51 PM PDT 24 |
512473790 ps |
| T997 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1859897716 |
|
|
Aug 06 05:39:46 PM PDT 24 |
Aug 06 05:39:47 PM PDT 24 |
35965720 ps |
| T998 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3999709444 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:48 PM PDT 24 |
15438971 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2187883237 |
|
|
Aug 06 05:39:28 PM PDT 24 |
Aug 06 05:39:30 PM PDT 24 |
55568237 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.268762842 |
|
|
Aug 06 05:39:30 PM PDT 24 |
Aug 06 05:39:31 PM PDT 24 |
78730931 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.318651883 |
|
|
Aug 06 05:39:07 PM PDT 24 |
Aug 06 05:39:09 PM PDT 24 |
81565730 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3279927726 |
|
|
Aug 06 05:39:47 PM PDT 24 |
Aug 06 05:39:51 PM PDT 24 |
159323366 ps |