SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 68909123 | 0 | T1 | 102 | T2 | 1047 | T3 | 97940 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 68908940 | 1 | T1 | 102 | T2 | 1047 | T3 | 97940 | ||||
values[1] | 16 | 1 | T73 | 1 | T74 | 1 | T137 | 1 | ||||
values[2] | 6 | 1 | T138 | 1 | T139 | 1 | T140 | 1 | ||||
values[3] | 100 | 1 | T73 | 2 | T74 | 1 | T75 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 68908952 | 1 | T1 | 102 | T2 | 1047 | T3 | 97940 | ||||
values[1] | 17 | 1 | T73 | 2 | T74 | 1 | T137 | 1 | ||||
values[2] | 9 | 1 | T74 | 1 | T141 | 1 | T142 | 1 | ||||
values[3] | 89 | 1 | T73 | 4 | T74 | 3 | T75 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 68908853 | 1 | T1 | 102 | T2 | 1047 | T3 | 97940 | ||||
auto[TlIntgErrCmd] | 99 | 1 | T73 | 2 | T74 | 4 | T75 | 4 | ||||
auto[TlIntgErrData] | 87 | 1 | T73 | 6 | T74 | 4 | T75 | 4 | ||||
auto[TlIntgErrBoth] | 84 | 1 | T73 | 2 | T74 | 2 | T75 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 361758 | 0 | T1 | 29 | T2 | 53 | T3 | 107 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 361582 | 1 | T1 | 29 | T2 | 53 | T3 | 107 | ||||
values[1] | 17 | 1 | T137 | 1 | T143 | 2 | T144 | 1 | ||||
values[2] | 4 | 1 | T143 | 1 | T141 | 1 | T145 | 1 | ||||
values[3] | 84 | 1 | T73 | 3 | T74 | 2 | T75 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 361567 | 1 | T1 | 29 | T2 | 53 | T3 | 107 | ||||
values[1] | 25 | 1 | T74 | 1 | T75 | 1 | T143 | 2 | ||||
values[2] | 8 | 1 | T75 | 1 | T141 | 1 | T146 | 1 | ||||
values[3] | 88 | 1 | T73 | 6 | T74 | 3 | T75 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 361488 | 1 | T1 | 29 | T2 | 53 | T3 | 107 | ||||
auto[TlIntgErrCmd] | 79 | 1 | T73 | 1 | T74 | 2 | T75 | 1 | ||||
auto[TlIntgErrData] | 94 | 1 | T73 | 4 | T74 | 6 | T75 | 6 | ||||
auto[TlIntgErrBoth] | 97 | 1 | T73 | 5 | T74 | 2 | T75 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |