Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13615423	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61164848

1

T1

1414

T2

2623

T3

110167

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37293203	1			T1	788		T2	1422		T3	60416
values[0x0]	17384627	1			T1	375		T2	705		T3	29450
values[0x1]	20102441	1			T1	408		T2	763		T3	31413

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6784727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67995544

1

T1

1488

T2

2748

T3

115589

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	399612	1			T1	31		T2	6		T3	624
valid_sources[0x01]	286401	1			T2	17		T3	405		T4	26
valid_sources[0x02]	279584	1			T1	1		T2	26		T3	680
valid_sources[0x03]	275027	1			T1	5		T2	3		T3	461
valid_sources[0x04]	291417	1			T2	5		T3	503		T4	30
valid_sources[0x05]	269535	1			T1	29		T2	4		T3	568
valid_sources[0x06]	290028	1			T1	6		T2	1		T3	469
valid_sources[0x07]	270377	1			T1	8		T2	18		T3	565
valid_sources[0x08]	271579	1			T1	1		T2	15		T3	591
valid_sources[0x09]	302193	1			T1	7		T2	5		T3	338
valid_sources[0x0a]	282632	1			T1	6		T2	4		T3	501
valid_sources[0x0b]	271628	1			T1	1		T2	43		T3	475
valid_sources[0x0c]	261128	1			T1	17		T2	7		T3	468
valid_sources[0x0d]	324297	1			T1	3		T2	24		T3	517
valid_sources[0x0e]	276063	1			T2	6		T3	429		T4	19
valid_sources[0x0f]	270182	1			T1	12		T2	26		T3	586
valid_sources[0x10]	315478	1			T2	20		T3	387		T4	25
valid_sources[0x11]	294776	1			T1	13		T3	350		T4	21
valid_sources[0x12]	300849	1			T1	5		T2	16		T3	415
valid_sources[0x13]	281101	1			T1	1		T2	4		T3	436
valid_sources[0x14]	288581	1			T2	3		T3	416		T4	15
valid_sources[0x15]	339954	1			T1	7		T3	486		T4	42
valid_sources[0x16]	293746	1			T2	32		T3	571		T4	41
valid_sources[0x17]	267742	1			T1	2		T2	23		T3	443
valid_sources[0x18]	260010	1			T3	521		T4	35		T5	12
valid_sources[0x19]	259655	1			T1	6		T2	46		T3	405
valid_sources[0x1a]	307121	1			T1	18		T2	10		T3	464
valid_sources[0x1b]	339975	1			T1	6		T3	517		T4	55
valid_sources[0x1c]	276359	1			T1	20		T3	540		T4	22
valid_sources[0x1d]	306322	1			T1	3		T3	540		T4	20
valid_sources[0x1e]	309048	1			T2	17		T3	461		T4	35
valid_sources[0x1f]	256718	1			T1	4		T2	13		T3	555
valid_sources[0x20]	282351	1			T2	12		T3	322		T4	14
valid_sources[0x21]	320010	1			T1	6		T2	5		T3	453
valid_sources[0x22]	268190	1			T1	2		T2	1		T3	476
valid_sources[0x23]	323782	1			T2	6		T3	376		T4	12
valid_sources[0x24]	263833	1			T2	25		T3	408		T4	12
valid_sources[0x25]	277611	1			T1	18		T3	391		T4	28
valid_sources[0x26]	272865	1			T1	9		T2	11		T3	343
valid_sources[0x27]	339424	1			T1	1		T2	9		T3	697
valid_sources[0x28]	258422	1			T2	14		T3	446		T4	18
valid_sources[0x29]	279247	1			T1	3		T2	18		T3	493
valid_sources[0x2a]	289396	1			T1	2		T2	3		T3	535
valid_sources[0x2b]	278995	1			T1	19		T3	487		T4	36
valid_sources[0x2c]	270048	1			T1	23		T3	238		T4	5
valid_sources[0x2d]	284470	1			T1	2		T2	7		T3	546
valid_sources[0x2e]	285369	1			T2	61		T3	476		T4	29
valid_sources[0x2f]	270573	1			T1	23		T2	10		T3	466
valid_sources[0x30]	286954	1			T3	374		T4	20		T5	8
valid_sources[0x31]	290533	1			T1	19		T2	5		T3	474
valid_sources[0x32]	275885	1			T1	4		T3	365		T4	58
valid_sources[0x33]	362966	1			T1	5		T2	8		T3	380
valid_sources[0x34]	266384	1			T1	15		T2	6		T3	471
valid_sources[0x35]	300463	1			T1	5		T2	7		T3	453
valid_sources[0x36]	320574	1			T2	4		T3	435		T4	8
valid_sources[0x37]	264151	1			T1	1		T2	17		T3	400
valid_sources[0x38]	307545	1			T2	3		T3	392		T4	29
valid_sources[0x39]	301939	1			T2	2		T3	530		T4	24
valid_sources[0x3a]	264116	1			T2	12		T3	585		T4	16
valid_sources[0x3b]	281347	1			T1	7		T2	13		T3	587
valid_sources[0x3c]	264587	1			T2	4		T3	506		T4	24
valid_sources[0x3d]	274806	1			T3	513		T4	25		T5	28
valid_sources[0x3e]	269237	1			T1	4		T2	10		T3	510
valid_sources[0x3f]	305596	1			T2	8		T3	539		T4	27
valid_sources[0x40]	284446	1			T2	4		T3	500		T4	17
valid_sources[0x41]	276945	1			T1	10		T2	15		T3	602
valid_sources[0x42]	271261	1			T1	1		T2	3		T3	556
valid_sources[0x43]	269984	1			T1	17		T2	4		T3	582
valid_sources[0x44]	336937	1			T1	19		T2	5		T3	417
valid_sources[0x45]	301099	1			T2	25		T3	425		T4	14
valid_sources[0x46]	263460	1			T1	3		T2	11		T3	474
valid_sources[0x47]	284904	1			T1	5		T2	6		T3	510
valid_sources[0x48]	282999	1			T1	7		T2	4		T3	507
valid_sources[0x49]	330535	1			T1	6		T2	1		T3	593
valid_sources[0x4a]	321572	1			T1	11		T2	30		T3	587
valid_sources[0x4b]	283382	1			T2	1		T3	427		T4	30
valid_sources[0x4c]	265478	1			T2	35		T3	475		T4	12
valid_sources[0x4d]	369200	1			T1	3		T3	418		T4	18
valid_sources[0x4e]	308888	1			T2	6		T3	650		T4	27
valid_sources[0x4f]	298464	1			T1	13		T2	12		T3	540
valid_sources[0x50]	309721	1			T1	7		T2	22		T3	487
valid_sources[0x51]	379796	1			T2	13		T3	441		T4	18
valid_sources[0x52]	275180	1			T1	5		T2	7		T3	311
valid_sources[0x53]	323875	1			T1	5		T2	3		T3	374
valid_sources[0x54]	271333	1			T1	1		T3	373		T4	25
valid_sources[0x55]	319899	1			T3	358		T4	19		T5	6
valid_sources[0x56]	286569	1			T2	11		T3	449		T4	35
valid_sources[0x57]	274338	1			T1	8		T2	5		T3	425
valid_sources[0x58]	286627	1			T3	438		T4	44		T5	6
valid_sources[0x59]	284138	1			T2	14		T3	291		T4	30
valid_sources[0x5a]	282137	1			T2	22		T3	433		T4	40
valid_sources[0x5b]	262608	1			T3	471		T4	17		T5	66
valid_sources[0x5c]	305058	1			T1	6		T2	3		T3	360
valid_sources[0x5d]	264148	1			T1	8		T2	5		T3	361
valid_sources[0x5e]	355635	1			T1	16		T2	2		T3	553
valid_sources[0x5f]	280007	1			T1	1		T2	2		T3	549
valid_sources[0x60]	289380	1			T1	4		T3	490		T4	21
valid_sources[0x61]	331026	1			T2	63		T3	359		T4	43
valid_sources[0x62]	340090	1			T1	18		T2	8		T3	462
valid_sources[0x63]	270944	1			T1	10		T2	4		T3	529
valid_sources[0x64]	303469	1			T2	6		T3	452		T4	10
valid_sources[0x65]	324973	1			T1	11		T3	422		T4	33
valid_sources[0x66]	268597	1			T1	7		T2	8		T3	361
valid_sources[0x67]	276874	1			T1	1		T2	5		T3	466
valid_sources[0x68]	270834	1			T1	8		T2	28		T3	429
valid_sources[0x69]	298025	1			T1	8		T2	4		T3	402
valid_sources[0x6a]	266376	1			T1	24		T2	10		T3	463
valid_sources[0x6b]	275614	1			T1	2		T2	5		T3	350
valid_sources[0x6c]	268768	1			T1	10		T2	16		T3	570
valid_sources[0x6d]	271662	1			T1	8		T2	7		T3	473
valid_sources[0x6e]	313559	1			T2	29		T3	430		T4	21
valid_sources[0x6f]	332981	1			T2	7		T3	517		T4	25
valid_sources[0x70]	324529	1			T2	5		T3	617		T4	31
valid_sources[0x71]	275742	1			T1	8		T2	5		T3	402
valid_sources[0x72]	322994	1			T1	31		T2	27		T3	401
valid_sources[0x73]	303213	1			T2	20		T3	489		T4	16
valid_sources[0x74]	263253	1			T1	8		T2	39		T3	591
valid_sources[0x75]	301079	1			T2	15		T3	392		T4	13
valid_sources[0x76]	272690	1			T1	13		T2	4		T3	274
valid_sources[0x77]	294365	1			T1	18		T2	18		T3	343
valid_sources[0x78]	299121	1			T1	14		T3	345		T4	33
valid_sources[0x79]	265668	1			T2	42		T3	436		T4	36
valid_sources[0x7a]	278425	1			T1	4		T2	15		T3	403
valid_sources[0x7b]	271899	1			T1	7		T2	36		T3	663
valid_sources[0x7c]	258299	1			T1	5		T2	11		T3	443
valid_sources[0x7d]	291111	1			T2	3		T3	488		T4	26
valid_sources[0x7e]	309501	1			T1	9		T2	3		T3	498
valid_sources[0x7f]	296714	1			T1	7		T2	1		T3	360
valid_sources[0x80]	284348	1			T1	13		T2	15		T3	349

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30489172

1

T1

709

T2

1297

T3

54894

values[0x0]

all_enables

biggest_size

15341858

1

T1

352

T2

656

T3

27696

values[0x1]

all_enables

biggest_size

15333818

1

T1

353

T2

670

T3

27577

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35070	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129240

1

T1

9

T2

16

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47119	1			T1	14		T2	25		T3	38
values[0x0]	56590	1			T1	7		T2	17		T3	33
values[0x1]	60601	1			T1	8		T2	11		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

137458

1

T1

12

T2

21

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	561	1			T16	2		T56	1		T19	4
valid_sources[0x01]	537	1			T3	2		T6	1		T19	4
valid_sources[0x02]	564	1			T19	15		T71	2		T152	1
valid_sources[0x03]	583	1			T3	1		T19	9		T71	1
valid_sources[0x04]	680	1			T16	2		T19	7		T71	2
valid_sources[0x05]	487	1			T57	1		T20	1		T153	5
valid_sources[0x06]	832	1			T5	1		T69	4		T18	1
valid_sources[0x07]	571	1			T19	10		T71	1		T20	3
valid_sources[0x08]	673	1			T56	1		T19	9		T71	2
valid_sources[0x09]	1091	1			T19	14		T71	1		T114	1
valid_sources[0x0a]	618	1			T3	1		T56	3		T154	1
valid_sources[0x0b]	683	1			T3	2		T16	2		T19	7
valid_sources[0x0c]	596	1			T16	1		T20	4		T21	10
valid_sources[0x0d]	556	1			T3	2		T16	1		T57	2
valid_sources[0x0e]	469	1			T19	1		T21	8		T155	1
valid_sources[0x0f]	593	1			T19	18		T71	1		T152	1
valid_sources[0x10]	508	1			T3	1		T19	11		T152	1
valid_sources[0x11]	841	1			T16	1		T19	3		T21	7
valid_sources[0x12]	785	1			T19	2		T71	3		T18	2
valid_sources[0x13]	919	1			T3	2		T19	4		T66	2
valid_sources[0x14]	607	1			T57	2		T19	1		T20	3
valid_sources[0x15]	482	1			T71	1		T156	1		T21	10
valid_sources[0x16]	663	1			T3	1		T16	2		T19	10
valid_sources[0x17]	763	1			T19	6		T154	1		T12	1
valid_sources[0x18]	561	1			T16	1		T19	2		T20	1
valid_sources[0x19]	566	1			T38	1		T16	2		T19	13
valid_sources[0x1a]	593	1			T3	1		T16	1		T19	2
valid_sources[0x1b]	543	1			T20	3		T21	10		T155	2
valid_sources[0x1c]	550	1			T16	2		T19	9		T71	1
valid_sources[0x1d]	391	1			T3	1		T57	1		T19	2
valid_sources[0x1e]	783	1			T79	1		T19	16		T154	1
valid_sources[0x1f]	547	1			T1	1		T19	10		T21	8
valid_sources[0x20]	839	1			T3	1		T19	8		T154	1
valid_sources[0x21]	511	1			T37	1		T19	6		T71	1
valid_sources[0x22]	856	1			T39	1		T16	1		T19	3
valid_sources[0x23]	547	1			T23	1		T16	1		T19	14
valid_sources[0x24]	536	1			T19	3		T71	1		T20	2
valid_sources[0x25]	785	1			T3	2		T19	1		T20	1
valid_sources[0x26]	731	1			T3	1		T16	1		T19	2
valid_sources[0x27]	571	1			T3	3		T16	2		T19	13
valid_sources[0x28]	752	1			T79	1		T16	1		T19	3
valid_sources[0x29]	582	1			T3	1		T16	1		T71	1
valid_sources[0x2a]	746	1			T19	3		T71	2		T12	1
valid_sources[0x2b]	572	1			T16	2		T19	4		T71	1
valid_sources[0x2c]	711	1			T19	4		T71	1		T12	2
valid_sources[0x2d]	672	1			T6	1		T16	1		T19	18
valid_sources[0x2e]	666	1			T3	1		T47	1		T69	1
valid_sources[0x2f]	1070	1			T19	7		T65	1		T51	1
valid_sources[0x30]	591	1			T57	1		T19	7		T71	2
valid_sources[0x31]	494	1			T16	1		T71	1		T21	6
valid_sources[0x32]	643	1			T16	1		T67	1		T71	1
valid_sources[0x33]	674	1			T1	2		T3	2		T16	1
valid_sources[0x34]	446	1			T3	1		T79	1		T19	14
valid_sources[0x35]	533	1			T19	9		T18	1		T99	3
valid_sources[0x36]	832	1			T19	5		T51	1		T18	1
valid_sources[0x37]	725	1			T55	7		T19	10		T20	4
valid_sources[0x38]	596	1			T16	1		T19	4		T18	1
valid_sources[0x39]	527	1			T3	1		T16	2		T19	3
valid_sources[0x3a]	641	1			T19	10		T152	1		T21	5
valid_sources[0x3b]	635	1			T3	1		T10	1		T16	3
valid_sources[0x3c]	662	1			T79	2		T16	1		T20	1
valid_sources[0x3d]	499	1			T16	2		T19	4		T51	1
valid_sources[0x3e]	484	1			T3	3		T16	1		T19	5
valid_sources[0x3f]	1068	1			T3	1		T19	2		T156	1
valid_sources[0x40]	493	1			T79	1		T16	2		T21	15
valid_sources[0x41]	554	1			T16	2		T19	7		T71	2
valid_sources[0x42]	506	1			T16	1		T19	4		T67	1
valid_sources[0x43]	673	1			T3	1		T57	1		T19	4
valid_sources[0x44]	743	1			T3	4		T22	65		T154	2
valid_sources[0x45]	787	1			T3	1		T16	1		T56	1
valid_sources[0x46]	505	1			T38	1		T19	10		T156	1
valid_sources[0x47]	674	1			T19	4		T71	1		T96	1
valid_sources[0x48]	724	1			T54	1		T19	2		T71	1
valid_sources[0x49]	767	1			T3	3		T19	7		T71	1
valid_sources[0x4a]	784	1			T19	1		T67	1		T71	1
valid_sources[0x4b]	677	1			T19	21		T20	3		T21	5
valid_sources[0x4c]	875	1			T3	1		T16	1		T57	1
valid_sources[0x4d]	527	1			T16	2		T19	4		T152	1
valid_sources[0x4e]	622	1			T19	15		T70	1		T71	2
valid_sources[0x4f]	461	1			T3	1		T16	1		T19	6
valid_sources[0x50]	604	1			T3	1		T57	1		T19	7
valid_sources[0x51]	792	1			T76	1		T79	1		T16	2
valid_sources[0x52]	521	1			T16	2		T19	4		T157	1
valid_sources[0x53]	661	1			T3	1		T16	4		T19	7
valid_sources[0x54]	626	1			T19	15		T71	2		T20	1
valid_sources[0x55]	853	1			T79	1		T71	1		T156	1
valid_sources[0x56]	569	1			T19	7		T20	3		T158	1
valid_sources[0x57]	556	1			T19	4		T65	1		T71	2
valid_sources[0x58]	634	1			T16	1		T57	1		T71	1
valid_sources[0x59]	693	1			T38	1		T16	1		T71	3
valid_sources[0x5a]	1031	1			T43	2		T71	1		T80	298
valid_sources[0x5b]	762	1			T57	2		T20	4		T21	8
valid_sources[0x5c]	580	1			T19	1		T67	2		T159	1
valid_sources[0x5d]	717	1			T38	2		T16	1		T19	12
valid_sources[0x5e]	957	1			T8	2		T38	1		T19	10
valid_sources[0x5f]	552	1			T16	1		T19	10		T71	2
valid_sources[0x60]	792	1			T57	1		T19	9		T67	1
valid_sources[0x61]	460	1			T57	1		T67	1		T71	1
valid_sources[0x62]	592	1			T6	1		T19	5		T71	1
valid_sources[0x63]	782	1			T19	10		T71	1		T20	1
valid_sources[0x64]	791	1			T19	1		T71	1		T21	7
valid_sources[0x65]	578	1			T2	53		T19	17		T71	1
valid_sources[0x66]	477	1			T3	2		T71	1		T20	1
valid_sources[0x67]	642	1			T55	1		T57	1		T19	11
valid_sources[0x68]	541	1			T44	9		T19	4		T67	1
valid_sources[0x69]	602	1			T3	1		T19	10		T71	4
valid_sources[0x6a]	651	1			T16	2		T19	1		T20	1
valid_sources[0x6b]	727	1			T19	12		T20	2		T160	1
valid_sources[0x6c]	661	1			T16	4		T19	2		T20	1
valid_sources[0x6d]	629	1			T19	1		T71	1		T20	2
valid_sources[0x6e]	464	1			T20	3		T158	1		T21	10
valid_sources[0x6f]	583	1			T3	1		T79	4		T16	2
valid_sources[0x70]	518	1			T152	1		T20	1		T21	5
valid_sources[0x71]	566	1			T79	1		T16	1		T55	2
valid_sources[0x72]	519	1			T16	1		T19	5		T152	2
valid_sources[0x73]	804	1			T79	2		T16	4		T19	1
valid_sources[0x74]	591	1			T43	3		T58	2		T19	5
valid_sources[0x75]	876	1			T76	1		T71	1		T156	1
valid_sources[0x76]	985	1			T3	4		T19	3		T47	2
valid_sources[0x77]	543	1			T16	2		T19	4		T71	2
valid_sources[0x78]	620	1			T19	10		T21	10		T45	4
valid_sources[0x79]	591	1			T3	2		T18	1		T20	1
valid_sources[0x7a]	721	1			T16	2		T161	17		T19	13
valid_sources[0x7b]	879	1			T6	5		T16	1		T19	3
valid_sources[0x7c]	677	1			T20	1		T21	10		T116	5
valid_sources[0x7d]	565	1			T3	2		T16	3		T19	9
valid_sources[0x7e]	649	1			T3	1		T71	6		T154	2
valid_sources[0x7f]	494	1			T3	2		T79	1		T57	1
valid_sources[0x80]	687	1			T3	1		T55	1		T44	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35197

1

T1

7

T2

9

T3

21

values[0x0]

all_enables

biggest_size

48145

1

T1

2

T2

6

T3

9

values[0x1]

all_enables

biggest_size

45898

1

T2

1

T3

5

T6

3