Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13246205

1

T1

10

T2

104

T3

8977

full_word

55662918

1

T1

92

T2

943

T3

88963

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68908853	1			T1	102		T2	1047		T3	97940
auto[TlIntgErrCmd]	99	1			T73	2		T74	4		T75	4
auto[TlIntgErrData]	87	1			T73	6		T74	4		T75	4
auto[TlIntgErrBoth]	84	1			T73	2		T74	2		T75	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31382548

1

T1

52

T2

521

T3

38601

auto[1]

37526575

1

T1

50

T2

526

T3

59339

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6299539	1			T1	6		T2	52		T3	3511
auto[TlIntgErrNone]	partial	auto[1]	6946415	1			T1	4		T2	52		T3	5466
auto[TlIntgErrNone]	full_word	auto[0]	25082886	1			T1	46		T2	469		T3	35090
auto[TlIntgErrNone]	full_word	auto[1]	30580013	1			T1	46		T2	474		T3	53873
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T75	1		T137	2		T143	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T73	1		T74	4		T75	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T140	1		T147	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T73	1		T75	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T73	1		T74	2		T75	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T73	5		T74	2		T75	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T138	1		T148	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T146	1		T139	1		T149	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T73	1		T74	2		T137	3
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T73	1		T75	2		T137	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T141	1		T146	1		T138	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T138	1		-	-		-	-