Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	787250	1			T1	12		T3	2852		T38	14076
auto[1]	10046309	1			T1	4		T2	458		T3	693
auto[2]	651779	1			T1	12		T2	1		T3	2616
auto[3]	9924278	1			T1	3		T2	487		T3	408

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14097700	1			T1	20		T2	762		T3	5033
auto[1]	2023865	1			T1	5		T2	93		T3	782
auto[2]	2037748	1			T1	6		T2	85		T3	662
auto[3]	3250303	1			T2	6		T3	92		T4	2

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8421506

1

T1

31

T2

946

T3

6560

auto[1]

12988110

1

T3

9

T5

3

T7

147

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	277716	1			T1	9		T3	2344		T38	11586
auto[0]	auto[0]	auto[1]	28888	1			T1	2		T3	249		T38	1160
auto[0]	auto[0]	auto[2]	28882	1			T1	1		T3	230		T38	1185
auto[0]	auto[0]	auto[3]	9311	1			T3	24		T38	135		T16	2
auto[0]	auto[1]	auto[0]	3187751	1			T1	2		T2	368		T3	372
auto[0]	auto[1]	auto[1]	336339	1			T1	1		T2	44		T3	267
auto[0]	auto[1]	auto[2]	322120	1			T1	1		T2	43		T3	35
auto[0]	auto[1]	auto[3]	70136	1			T2	3		T3	19		T4	1
auto[0]	auto[2]	auto[0]	232098	1			T1	6		T3	2151		T38	10748
auto[0]	auto[2]	auto[1]	24179	1			T1	2		T2	1		T3	248
auto[0]	auto[2]	auto[2]	27872	1			T1	4		T3	197		T38	773
auto[0]	auto[2]	auto[3]	7682	1			T3	16		T38	80		T22	4
auto[0]	auto[3]	auto[0]	3143819	1			T1	3		T2	394		T3	157
auto[0]	auto[3]	auto[1]	317145	1			T2	48		T3	18		T4	4
auto[0]	auto[3]	auto[2]	335415	1			T2	42		T3	200		T4	3
auto[0]	auto[3]	auto[3]	72153	1			T2	3		T3	33		T4	1
auto[1]	auto[0]	auto[0]	14887	1			T3	5		T38	8		T69	756
auto[1]	auto[0]	auto[1]	65857	1			T69	3441		T71	3		T114	2473
auto[1]	auto[0]	auto[2]	65972	1			T38	2		T69	3383		T71	2
auto[1]	auto[0]	auto[3]	295737	1			T84	1		T69	14802		T70	1
auto[1]	auto[1]	auto[0]	3616142	1			T5	2		T7	70		T10	55163
auto[1]	auto[1]	auto[1]	621959	1			T7	9		T10	5566		T110	7992
auto[1]	auto[1]	auto[2]	591100	1			T7	2		T10	5515		T110	8315
auto[1]	auto[1]	auto[3]	1300762	1			T7	1		T10	568		T110	800
auto[1]	auto[2]	auto[0]	11452	1			T3	4		T38	11		T69	634
auto[1]	auto[2]	auto[1]	51194	1			T38	2		T69	3112		T71	2
auto[1]	auto[2]	auto[2]	53874	1			T54	1		T69	2231		T71	3
auto[1]	auto[2]	auto[3]	243428	1			T84	1		T69	10171		T114	7607
auto[1]	auto[3]	auto[0]	3613835	1			T7	55		T10	55021		T110	83790
auto[1]	auto[3]	auto[1]	578304	1			T7	6		T10	5561		T110	8372
auto[1]	auto[3]	auto[2]	612513	1			T7	4		T10	5594		T110	8373
auto[1]	auto[3]	auto[3]	1251094	1			T5	1		T10	564		T110	871