Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	345740697	184295	0	0
ctrl_regwen_rd_A	345740697	3351	0	0
exec_rd_A	345740697	3207	0	0
exec_regwen_rd_A	345740697	3351	0	0
readback_rd_A	345740697	2413	0	0
readback_regwen_rd_A	345740697	2060	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345740697	184295	0	0
T19	52890	2568	0	0
T20	0	814	0	0
T21	0	2251	0	0
T31	0	1577	0	0
T45	0	4818	0	0
T47	17786	0	0	0
T50	0	2749	0	0
T60	0	6925	0	0
T64	191583	0	0	0
T65	8534	0	0	0
T66	3395	0	0	0
T67	85980	0	0	0
T68	154126	0	0	0
T69	150811	0	0	0
T70	16370	0	0	0
T81	0	11304	0	0
T82	0	2088	0	0
T83	0	3708	0	0
T84	16697	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345740697	3351	0	0
T31	0	117	0	0
T45	156634	339	0	0
T46	0	236	0	0
T120	0	533	0	0
T121	0	162	0	0
T122	0	51	0	0
T123	0	426	0	0
T124	0	62	0	0
T125	0	76	0	0
T126	0	1	0	0
T127	5794	0	0	0
T128	243389	0	0	0
T129	55434	0	0	0
T130	15224	0	0	0
T131	1462	0	0	0
T132	172801	0	0	0
T133	9606	0	0	0
T134	215607	0	0	0
T135	321547	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345740697	3207	0	0
T31	0	101	0	0
T45	156634	367	0	0
T46	0	155	0	0
T120	0	575	0	0
T121	0	182	0	0
T122	0	25	0	0
T123	0	380	0	0
T124	0	56	0	0
T125	0	65	0	0
T126	0	4	0	0
T127	5794	0	0	0
T128	243389	0	0	0
T129	55434	0	0	0
T130	15224	0	0	0
T131	1462	0	0	0
T132	172801	0	0	0
T133	9606	0	0	0
T134	215607	0	0	0
T135	321547	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345740697	3351	0	0
T31	0	143	0	0
T45	156634	361	0	0
T46	0	212	0	0
T120	0	572	0	0
T121	0	159	0	0
T122	0	33	0	0
T123	0	369	0	0
T124	0	109	0	0
T125	0	83	0	0
T126	0	4	0	0
T127	5794	0	0	0
T128	243389	0	0	0
T129	55434	0	0	0
T130	15224	0	0	0
T131	1462	0	0	0
T132	172801	0	0	0
T133	9606	0	0	0
T134	215607	0	0	0
T135	321547	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345740697	2413	0	0
T31	0	108	0	0
T45	156634	354	0	0
T46	0	126	0	0
T120	0	598	0	0
T121	0	176	0	0
T122	0	22	0	0
T123	0	498	0	0
T124	0	62	0	0
T125	0	34	0	0
T127	5794	0	0	0
T128	243389	0	0	0
T129	55434	0	0	0
T130	15224	0	0	0
T131	1462	0	0	0
T132	172801	0	0	0
T133	9606	0	0	0
T134	215607	0	0	0
T135	321547	0	0	0
T136	0	14	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	345740697	2060	0	0
T31	0	104	0	0
T45	156634	214	0	0
T46	0	121	0	0
T120	0	504	0	0
T121	0	159	0	0
T122	0	26	0	0
T123	0	385	0	0
T124	0	67	0	0
T125	0	46	0	0
T126	0	2	0	0
T127	5794	0	0	0
T128	243389	0	0	0
T129	55434	0	0	0
T130	15224	0	0	0
T131	1462	0	0	0
T132	172801	0	0	0
T133	9606	0	0	0
T134	215607	0	0	0
T135	321547	0	0	0